ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<ere> is there separate chat for gowin?
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<Sarayan> ERROR: Multiple edge sensitive events found for this signal!
<Sarayan> that means multiple writes?
<Sarayan> it's setting is in a always @(posedge clk32, negedge porb, negedge resb) begin
<Sarayan> og.kervella.org/gstmcu.v signal ixdma, comes from AtariST_Mister
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<jix> Sarayan: AFAICT it's just that both porb as well as resb cause an async reset of ixdma, but yosys' FF cells can only have one ALOAD input
<jix> (or an async reset instead of async load, but still same limitation)
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<jix> since the actual modelled behavior is just a level sensitive async reset when either of them is low, it's possible to use a single FF and connect the and of both of them to the async reset input
<Sarayan> thanks, gonna try that
<jix> wait, maybe it's not this
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<Sarayan> yeah, doesn't change a thing
<Sarayan> fwiw I'm trying to build a sim using og.kervella.org/yosys.sh
<Sarayan> that coe overuses edges
<Sarayan> code
<jix> (the "wait, ..." was just me not noticing a typo I had made)
<jix> I haven't really used cxxrtl myself, but when the design does lot of async stuff it might not work as is due to stuff like this https://github.com/YosysHQ/yosys/issues/3549
<jix> the good news is that (depending on how the design uses async stuff) you might still be able to simulate it by using async2sync or clk2fflogic to convert it to a sync design before running it through cxxrtl
<jix> so the frontend does have the logic to combine multiple level sensitive resets (I also did vaguely remember seeing this), it just doesn't recognize the particular pattern used
<Sarayan> oh cute
<Sarayan> much thanks
<Sarayan> yep, once I've added the missing modules cxxrtl generates the .cc, beautiful
<jix> the two ways that work also do match IEEE 1364.1 "Standard for Verilog Register Transfer Level Synthesis" while the original doesn't
<jix> not that yosys is limiting itself to that, lots of real world RTL doesn't strictly follow that and other tools do support more too, but following that probably still is a good way to make sure synthesis works and matches across tools
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<Sarayan> that all confirms my clear preference for amaranth
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<lofty> ere: #yosys-apicula
<ere> lofty: thanks
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