ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<Guest8> Hi ,
<Guest8> How to set dont use library cells for some library cells based on pattern : like set_dont_use /XOR3
<Guest8> Using version : Yosys 0.23+45 (git sha1 a64ed82, clang 10.0.0-4ubuntu1 -fPIC -Os)
<Guest8> Thanks
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<bjonnh> Hi, I'm trying to compile this verilog module: https://gist.github.com/bjonnh/16f64872e62fb86ef429c98abce330fc
<bjonnh> and I get top.v:37: ERROR: syntax error, unexpected '(', expecting OP_CAST
<bjonnh> This seems to be related to those two entries with signed( on them. If I comment that code, I get an error on line 51 about ERROR: syntax error, unexpected TOK_CONSTVAL
<bjonnh> To me this all look like normal verilog I can't really get what's wrong with it.
<tnt> b'00 should be 2'b00
<tnt> signed should be $signed AFAIR
<bjonnh> Thanks, I found that here: https://github.com/AndrewJones-PSU/I2S2Test I suppose they use some kind of vendor specific verilog?
<tnt> or systemverilog
<bjonnh> oh so systemverilog IS different from verilog
<bjonnh> I wasn't sure as I gave the ECP PLL example (that is in systemverilog) directly to yosys and it was happy with it
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<bjonnh> tnt: Thanks, that works now.
<bjonnh> Well... still no sound out, but at least that compiles
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