ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<RowanG[m]> I'm looking at the DSP on the ECP5
<RowanG[m]> and I don't understand why there are 4 clock inputs
<RowanG[m]> Does anyone know how that works?
<RowanG[m]> The only thing I can imagine is allowing a single DSP to be used in 4 domains at the same time depending on clock enable. But that's not someting I have ever come across
<mwk_> the DSP has 4 registers: A, B, pipeline, output
<mwk_> each of them can have independent CLK/CE/RST
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