ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<radens`> Hello! I'm trying to learn verilog and wanted to generate something like a circuit diagram to make sure I'm understanding everything. I did a ripple carry adder tutorial on eda and then I read that I could use a command like `yosys ./rcc.v -p 'show -prefix rcc -colors 2 -width -format dot'` to generate a diagram, but I don't see the outputs of
<radens`> the tff blocks(wrong word?) being forwarded to the next blocks: https://imgur.com/a/2q5RSOK
<tpb> Title: Imgur: The magic of the Internet (at imgur.com)
<radens`> Tutorial in question: https://www.edaplayground.com/s/example/351
<tpb> Title: Ripple Carry Counter - EDA Playground (at www.edaplayground.com)
<radens`> I was hoping to generate a diagram like the first frame of this video: https://www.youtube.com/watch?v=eXb8prknDKg&list=PLntFkFHRTxmLEv5MJN3oDvhd-5z3L5Rhi
<radens`> What I got feels more like an ast.
<Forty-Bot> radens`: use heirarchy first
<Forty-Bot> so like `hierarchy -top ripple_carry_counter; prep; opt; show`
<radens`> Forty-Bot that's more like it, thanks
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