ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
ec_ has joined #yosys
ec_ has quit [Ping timeout: 240 seconds]
emeb_mac has quit [Quit: Leaving.]
anticw has quit [Ping timeout: 255 seconds]
gordonDrogon has quit [Ping timeout: 240 seconds]
anticw has joined #yosys
gordonDrogon has joined #yosys
gordonDrogon has quit [Ping timeout: 246 seconds]
gordonDrogon has joined #yosys
Ekho has quit [Remote host closed the connection]
gordonDrogon has quit [Ping timeout: 276 seconds]
Ekho has joined #yosys
gordonDrogon has joined #yosys
kraiskil has joined #yosys
kraiskil has quit [Ping timeout: 240 seconds]
emeb_mac has joined #yosys
<ikskuh> heya o/
<ikskuh> is it normal to generate verilog code for certain repetetive tasks like a bus interconnect?
<Sarayan> verilog is not normal
<ikskuh> well, that's true
FabM has joined #yosys
FabM has joined #yosys
FabM has quit [Changing host]
<qball> lol
<lambda> otoh generating it is the most normal/sane thing you can do with verilog
ec_ has joined #yosys
ec_ has quit [Ping timeout: 240 seconds]
ec_ has joined #yosys
ec_ has quit [Ping timeout: 240 seconds]
ec_ has joined #yosys
FabM has quit [Quit: Leaving]
ec_ has quit [Ping timeout: 240 seconds]
nonchip has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
nonchip has joined #yosys