ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<ikskuh> heya o/
<ikskuh> still hacking around with yosys/verilog and i'm wondering: how can i include a initialization for a ROM?
<ikskuh> should i just add a huge case() with all options? that doesn't really sound smort
<tnt> google $readmemh
<ikskuh> thx :)
<ikskuh> i kinda assumed readmemh would only run during simulation
<ikskuh> and not for synthesis
<tnt> it works in synthesis (as long as it's done in a `initial` block of course, can't start doing it "dynamically" ...)
<ikskuh> well, that's obvious :D
<ikskuh> but perfect, thanks :)
<ikskuh> font rom, here i come!
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