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<Guest82>
Where to find ABC's latest operating manual
<Guest82>
how to use abc9
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<lofty>
Guest82: uh, Yosys wraps a lot of ABC for you, but run yosys-abc directly and you can run help to get a list of commands and then run each command with -h to see what it does
<lofty>
As for ABC9, it's probably best to leave that to the Yosys ABC9 pass
<Guest82>
there is no aig
<Guest82>
when use abc9
<Guest82>
For example, command line "twoexact -g -I 5 -N 12 169AE443"
<Guest82>
synthesizes the smallest circuit composed of two-input gates
<Guest82>
for the only NPN class of 5-input functions that requires 12 gates;
<Guest82>
all other functions can be realized with 11 two-input gates or less
<Guest82>
this command
<Guest82>
What is the format of the truth table
<Guest82>
twoexact [-INT <num>] [-aogvh] <hex>
<Guest82>
exact synthesis of multi-input function using two-input gates
<Guest82>
-I <num> : the number of input variables [default = 0]
<Guest82>
-N <num> : the number of two-input nodes [default = 0]
<Guest82>
-T <num> : the runtime limit in seconds [default = 0]
<Guest82>
-a : toggle using only AND-gates (without XOR-gates) [default = no]
<Guest82>
-o : toggle using additional optimizations [default = no]
<Guest82>
-g : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = no]
<Guest82>
For example, command line "twoexact -g -I 5 -N 12 169AE443"
<Guest82>
synthesizes the smallest circuit composed of two-input gates
<Guest82>
for the only NPN class of 5-input functions that requires 12 gates;
<Guest82>
all other functions can be realized with 11 two-input gates or less
<lofty>
0x169AE443 is 32-bit, AKA 2**5-bit, so for each bit N, the result of the truth table when the 5 inputs are N is the value of bit N of the truth table
<lofty>
But there's something more important you should note
<lofty>
"Note that this is a logic optimization pass within Yosys that is calling ABC
<lofty>
internally. This is not going to "run ABC on your design". It will instead run
<lofty>
design as BLIF file with write_blif and then load that into ABC externally if
<lofty>
output when passing an ABC script that writes a file. Instead write your full
<lofty>
ABC on logic snippets extracted from your design. You will not get any useful
<lofty>
you want to use ABC to convert your design into another format."
<lofty>
From `yosys -p "help abc"`
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<Guest82>
I understand, thanks
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<Guest82>
abc -g gates
<Guest82>
2. Executing ABC pass (technology mapping using ABC).
<Guest82>
2.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
<Guest82>
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
<Guest82>
Don't call ABC as there is nothing to map.
<Guest82>
Removing temp directory
<Guest82>
output always 0
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<lambda>
gatecat: hey, any idea how to debug "ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc." from nextpnr-xilinx? full log here, either it's not giving me any additional information about the problem, or I'm not understanding it: https://dpaste.com/C62HXJTKM.txt
<gatecat>
really hard to say, sorry
<gatecat>
don't have the bandwidth for anything tech for at least a week
<gatecat>
it's either a bug in the timing data or a combinational loop, real or fake
<lambda>
alright, I'll try to narrow it down as best as I can, thanks :)
<gatecat>
might take a while but you could probably get something going with bugpoint
<gatecat>
(and the ability to call external commands by prefixing them with ! in a Yosys script to call nextpnr)
<lambda>
good idea
<cr1901>
>don't have the bandwidth for anything tech <-- this is a mood