<nonchip>
hi, i'm trying to adapt this thing to my project (which uses verilog instead of GHDL): https://hackaday.io/project/180839-vhdlverilog-to-discrete-logic-flow but i noticed that there's no `SUBCKT` definition in my resulting spice netlist (the file literally starts with `X0` after a comment about the yosys version), and assuming that GHDL would have defined that somehow i'm wondering if/how i can instead tell yosys to emit that line?
<nonchip>
alternatively, if anyone has suggestions for other "verilog to discrete logic" synthesis approaches i could try (apart from "draw by hand"), that would also be appreciated :)
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<josuah>
nonchip: you can generate a PDF diagram that can help
<josuah>
nonchip: but that is not a complete exhaustive diagram
<josuah>
nonchip: there are blocks with things that not exist "as-is" in gateware, like a multiplication, etc.
<josuah>
nonchip: so you would have to insert "discrete logic for basic block $x" here and there
<nonchip>
yeah i'm doing that currently, even fits rather readable on an A4 page since i ran `opt -full -purge -fine`, but yeah from there it's either print it out and draw on it, or i guess figure out some kinda techmap for turning things into mosfets :P
<josuah>
maybe the .dot files can be edited afterhand for this
<nonchip>
it's actually rather tame: a few tribufs, half of them are really just open drain pins, a few dff, a few mux, a few logic_*s
<nonchip>
and a few sections that are already ICs i know, wondering how to best optimize those away (e.g. i got a binary counter and a few registers that are currently being represented as various kinds of DFFs)
<josuah>
oh, actually use it with spice! I misread that at first
<nonchip>
i think that's possible with ABC and a custom techmap?
<josuah>
my knowledge of yosys toolchain might be lacking a bit to answer that though :S
<nonchip>
i just need essentially a "hey that bunch of cells is actually that IC over there" map file, shouldn't be too hard after i figure out *which* of the 50 million map functions to use :P
<nonchip>
my design (after optimization) fits on an A4 page, it's not too hard to write that map by hand really, but i'd rather then yosys give me something i can feed to e.g. kicad than actually plonking down all the chips by hand because i have rather wide parallel busses
<josuah>
oh, so it permits you to check if there is an ASIC matching the RTL design you need?
<nonchip>
i *think* that's what the ABC mapper is for but not 110% sure
<nonchip>
optionally replace all the `<16>`s by any bus width you might like, because it's flexible like that. it's a suuuper small and even suuuuuuperer dumb transport-triggered CPU core essentially. it literally just reads 2 addresses, copies from the first to the second, except if the second was 0, then it copies into the program counter (= jump)
<josuah>
nonchip: are you doing a discrete component processor?
<nonchip>
no ALU, conditional logic or anything else, it doesn't even read opcodes, literally just the arguments for the only thing it does: copying from/to 2 addresses.
<nonchip>
yup :)
<nonchip>
want to make an educational kinda "this is what you need to execute a thing" PCB with discrete components and lots of LEDs to view the bits in realtime, and any actual logic/maths/etc will just be hooked up as peripherals to the main bus in addition to presumably some memory.
<nonchip>
so essentially it's a 1-instruction-execute-cycle-on-a-board :P
<nonchip>
because technically that's all you need. add an ALU of your choosing on the bus, and just use that to overwrite the address of a jump target conditionally, and there's your turing completeness :P
<josuah>
this, on a room full of curious people, would likely get a lot of attention
<josuah>
a turing machine in a very small nutshell!
<nonchip>
yeah that was one inspiration for that
<nonchip>
fun fact my cpu can't even halt :P for that you need to either make a peripheral for control stuff like that (maybe also for selecting the clock speed or whatever), or jump into an endless loop :D
<josuah>
an ALU of your choosing on the bus
<josuah>
an ALU... as a peripheral! :D yay!
<josuah>
the principle of a microkernel, but for hardware
<josuah>
interesting
<nonchip>
i wonder if this cpu could also be implemented using a DMA controller with hardwired instructions...
<josuah>
is that not some sort of DMA already?
<nonchip>
essentially yeah
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