ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<corecode> oh i didn't realize that yosys can synthesize for efinix fpgas
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<rowang077[m]> What are "SIOLOGIC" resources?
<rowang077[m]> I find I use quite a few of them in my design
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<rowang077[m]> Specifically for ECP5
<rowang077[m]> in the ECP5 high-speed IO manual I can find that there is a difference between IOLOGIC and SIOLOGIC
<rowang077[m]> s/ECP5/ECP3/
<rowang077[m]> But there is no mention of them in the same document for ECP5
<gatecat> SIOLOGIC are for the top/bottom sides, IOLOGIC are for the left/right sides
<gatecat> no idea what 'S' stands for, you'd have to ask lattice :D
<gatecat> they'll be used for each pin that has a DDR I/O or a packed I/O register
<rowang077[m]> Ah allright
<rowang077[m]> so there is no (known) functional difference between IOLOGIC and SIOLOGIC?
<rowang077[m]> it's just different locations on the fabric
<gatecat> the IOLOGIC are more feature-complete
<gatecat> but which of the two are used depend on the IO pin you're using
<gatecat> the [S]IOLOGIC blocks are directly tied to a specific IO
<rowang077[m]> Clear. Thx!
<rowang077[m]> Do you now how I can understand why a asynchronous path is seen in nextpnr
<rowang077[m]> From what I can tell in my code there shouldn't be an async path
<rowang077[m]> I have uploaded the code here: https://gist.github.com/rowanG077/7b5c561c88c2e5a1873802fbd4716bbe
<rowang077[m]> But it's generated so it's not to easily readable
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<gatecat> I think it's something to do with how the DIRECTION pin on the iodelay has been implemented#
<gatecat> inside nextpnr
<gatecat> not anything to worry about - tbh the async paths aren't that meaningful in general atm
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