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<pepijndevos[m]>
I've started a page on the Yosys wiki with the goal of documenting which FPGA families support which primitives. I've added Apicula, which I maintain, so if people think it's a good idea it could also contain other FPGA projects. https://github.com/YosysHQ/yosys/wiki/FPGA-family-feature-matrix
<Sarayan>
what's a long wire?
<pepijndevos[m]>
Some FPGAs have wires that cross a significant part of the grid, rather than going to adjacent tiles.
<Sarayan>
oh, and they're special?
<sorear>
i predict that table will grow a lot of rows and n/a cells, as well as debate over whether feature X in fpga Y actually corresponds to table row Z
<Sarayan>
(wire length in the cyclone v can be 2, 3, 4, 6, 12 or 14 tiles, there's not really any distinction)
<Sarayan>
die tile size goes from 49x40 up to 122x116 just to put things in perspective
<Sarayan>
clock grid has bigger stuff, including 16 global clocks that go just everywhere
<Sarayan>
it's funky stuff :-)
<pepijndevos[m]>
Hmmm yea the table items will have to evolve to accomodate what FPGA families actualy have
<pepijndevos[m]>
I'm fine with folding long wires under global/clock routing
<whitequark>
even ice40 has long wires (span4/span12)
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<cr1901>
Can we have a yellow "caution" symbol for "it should work but not well-tested"?
<pepijndevos[m]>
Sure
<pepijndevos[m]>
Should also have a "partial" symbol probably
<cr1901>
traffic cone?
<pepijndevos[m]>
ohhhh yea
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<cr1901>
pepijndevos[m]: No traffic cone emoji. This is close enough IMO