kristianpaul has quit [Read error: Connection reset by peer]
emeb_mac has quit [Ping timeout: 268 seconds]
kristianpaul has joined #yosys
FabM has joined #yosys
FabM has joined #yosys
FabM has quit [Changing host]
dlobato has joined #yosys
vidbina has joined #yosys
vidbina has quit [Ping timeout: 268 seconds]
dlobato has quit [Ping timeout: 268 seconds]
piegames has quit [Ping timeout: 260 seconds]
piegames has joined #yosys
<bluesceada>
There is a problem with newer yosys versions when accessing regs like din[(i<<3)+:8] ... while din[(i*8)+:8] works correctly
<bluesceada>
it also worked in older yosys versions (some version from FPGAwars from 2019), but not in the recent ones included in oss-cad-suite over the last 6 months or so
<bluesceada>
We might bisect this when we find time, but not now ..
<mwk>
do you have a sample?
<mwk>
(I dont' mind looking at a huge one)
<bluesceada>
not sure if I should just give that out, let's see...
<mwk>
can you reduce it to something you can show me?
<bluesceada>
Not now, but I can only give it to you, should just not be totally public here
<bluesceada>
mwk, I can send you the link in query
<tpb>
Title: module test( input wire [31:0] a, input wire [1:0] b, output w - Pastebin.com (at pastebin.com)
<mwk>
right, hold on
<mwk>
this is one of these unfortunate moments when I have to consult the Verilog standard to figure out if it's really a bug, or just a correctly implemented Verilog pitfall
<tnt>
yosys's behavior is correct from my reading.
<mwk>
yeah, mine as well
<mwk>
this is a Verilog pitfall IMO
dlobato has joined #yosys
<mwk>
don't see the exact place in Verilog standard where it says that bit select index width is self-determined, but I don't really see it being any other way
<bluesceada>
The question is if you want to handle it like a commercial tool as lattice icecube, or not
<bluesceada>
We might have also used this in Xilinx Vivado successfully (but not sure)
<tnt>
mwk: mmm, I guess 'integer expression' could mean 32b.
<bluesceada>
but yeah if you write (b << 3) ... I guess one should not expect an automatic bit width extension of b --- that is also why we realized quite quickly that this could be a problem
<mwk>
current yosys behavior is correct, I'm afraid
<bluesceada>
That's one of the situations in which VHDL's strictness is better, I guess
<mwk>
"like a commercial tool" is ill-defined in the first place
<bluesceada>
mwk, of course, I have no specific opinion on this, I am not saying yosys should change it
<mwk>
I can take a bet there's a different commercial tool that behaves like yosys does
<mwk>
... this is the usual outcome of attempting to use many parts of Verilog
<bluesceada>
Yes, icecube isn't really widely used
<bluesceada>
If widely used tools of Xilinx/Intel/Synopsys/Cadence/Mentor would do the extension in the index I would say yosys should be too (if the Verilog standard is not 100% clear on that)
<mwk>
okay
<mwk>
Verilog standard wasn't helpful
<mwk>
but SystemVerilog is very clear on this
<bluesceada>
is there a way to set which standard to follow in yosys? many commercial tools often have that option
<mwk>
"The bit can be addressed using an expression that shall be evaluated in a self-determined context."
<mwk>
not really, no
<mwk>
there's an option to enable or disable systemverilog, but it basically just disables features, it doesn't *change* anything
<mwk>
also: given that Verilog has no text at all on the subject, but also absolutely no reason to infer anything but self-determined behavior by default, I'm just going to go with the "it should always be self-determined" interpretation
<mwk>
SystemVerilog text clarifying the intended meaning
<bluesceada>
so and for you "self-determined" means to not extend the width? That doesn't sound clear to me, to be honest
<mwk>
that's an actual well-defined term from the standard
<bluesceada>
OK
<mwk>
for a shift expression like this, it very definitely means the width is taken directly from left operand