ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<cr1901> read_verilog only works for full modules. Is it possible to take a selection and create a separate module so that I can write out the subset of the entire input cone of an output signal as a module?
<mwk> design -save, flip selection, remove selection, write what remains to .v file, design -load
<mwk> (assuming you mean write_verilog)
<cr1901> Yes write_verilog is what I meant
<cr1901> I came across a design that synthesizes for machxo2 but the post-synth doesn't match pre-synth. And I got a miter to fail induction w/ the desired signal
<mwk> ... that's worrying
<cr1901> It's probably something I did
<mwk> how exactly are you doing the post-synth test?
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<cr1901> You want me to give you my exact inputs?
<mwk> mhm, so it's not a P&R issue, okay
<cr1901> Right, this happens during packing
<cr1901> sorry for not making that clear
<mwk> packing?
<cr1901> FFs/LUTs => SLICEs
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<mwk> oh, so you're tracking down a nextpnr bug?
<cr1901> yes
<mwk> okay, was worried there was something broken in general yosys code for a moment
<cr1901> But Idk where to even look without using yosys to help me
<cr1901> There's no way I'm gonna be able to keep track of the entire post-synth design in my head, even for something as simple as a UART
<mwk> ... last time I was in that situation, I ended up tracking down a JSON parser bug with an oscilloscope
<cr1901> That is one hell of a sentence you just wrote.
<cr1901> Anyways I'm giving up for the night
<cr1901> What are the commands for flipping/removing selection? And is the design -save part necessary?
<mwk> design -save is only necessary if you want to get the original back later
<mwk> the remove command is spelled `delete <selection>`
<mwk> and as for flipping: append %n when constructing the selection
<cr1901> tyvm... night! :)
<mwk> night
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<famubu> Hi. Is yosys more comfortable working with verilog when compared to vhdl? Is there something like that? (I'm new to yosys)
<famubu> The manual mentions in the history section of the yosys manual that the developers prefered verilog over vhdl.
<famubu> And in Chapter 4 (Implementation overview), it is mentioned that a VHDL frontend is in development.
<famubu> But the last commit was 6 years ago.
<gatecat> famubu: https://github.com/ghdl/ghdl-yosys-plugin is considerably newer and more complete
<famubu> gatecat: Thanks!
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<cr1901> Okay, I'm awake. And my current verdict is I don't want to work on finding the bug today. So I won't :).
<cr1901> Thank goodness for .yosys_history
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