<dormito>
I've notice that when I do "read_verilog -sv ${verilog-source-file}" it prints "Executing Verilog-2005 frontend", and then seems to choke on any usage of interfaces (says the signals implicitly defined, eventhough it already parsed it in the module ports). Am I invoking systemverilog incorrectly?
<Sarayan>
the current sv parser has limits
<dormito>
the README.md says it supports interfaces and mod ports... is that qualified or incorrecT?
<Sarayan>
I'm not entirely sure of the limits, I know one is missing non-packed structures
<Sarayan>
but I'm certain it's not yet fully handling sv-for-synthesis
<dormito>
Hmmm maybe the readme should be updated then (since it seems to pretty clearly say some certain systemverilog features are supported). I've distilled the reproduction down to a 23-line hdl file anyone wants to see how to invoke it.
<Sarayan>
would probably be interesting to implement what's missing in that area
<Sarayan>
as far as I can tell it's a case of "nobody has implemented it yet", not something deliberate :-)