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<cyndis>
tagr: How was the limitation of IOVAs to 39 bits supposed to work on Tegra194? I'm only seeing your device tree patch to add the memory-controller node with dma-ranges
<cyndis>
is there perhaps some magic in the interconnects?
<cyndis>
the problem I'm seeing is that with context devices, I'm getting full 40 bit IOVAs currently
<cyndis>
they are not platform devices so if the restriction is coming though device tree, that is not surprising
<tagr>
yeah, there's some magic in the core OF code that sets the bus' DMA limit using dma-ranges
<cyndis>
MC is not a parent of all of our devices though so I wasn't expecting that to apply
<tagr>
cyndis: of_dma_configure_id() is where this happens
<tagr>
it's a DMA parent of all the device, though
<tagr>
that relationship is created via the interconnects property, and that's also why the naming is a bit inconsistent in some places, because in order for this to work, there has to be one interconnect path named "dma-mem"
<cyndis>
I see, so it's interconnects magic
<cyndis>
I do use of_dma_configure_id for the context devices so I guess if I add an interconnects property it probably will work
<cyndis>
though we actually need to limit it to 38 bits since NVENC has a bug where it cannot use the last bit..
<cyndis>
also the context devices are not real devices so they are not really connected to the memory-controller
<cyndis>
maybe I'll just set the DMA mask directly
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<tagr>
they are connected via their parent, right, so perhaps just inherit the DMA mask from the parent, which I guess is the host1x device
<tagr>
but yeah, if we need to special-case for NVENC anyway, might as well set it explicitly (or you could perhaps do it conditionally for only the NVENC context device)
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<cyndis>
the issue is that there is no "NVENC context device", since each process gets a context and we don't know if they're going to use nvenc or not
<cyndis>
but, this seems to work, so I think it's good
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