15:24 <tagr> digetx: have you seen this: https://lore.kernel.org/dri-devel/20210914093515.260031-1-maxime@cerno.tech/

15:25 <tagr> it kind of reminded me of the work you're currently doing on Tegra, except that it seems to be taking a bit of a short-cut

15:25 <tagr> i.e. your solution seems a bit more robust and standard

15:45 <digetx> tagr: I saw it while was skimming through ML earlier today, it's indeed similar to the memory bandwidth and genpd performance state management that we use; long time ago, before ICC existed, I was considering a similar clk solution for the EMC rate management; it may be good enough for RPI if nothing else depends on the clock rate

15:59 <tagr> yeah, that's why I'm bringing it up, I suspect that they may be looking at only part of the picture and choose an inadequate solution

16:12 <digetx> I'm not familiar with the hardware in question; SoC power management is very hw-specific, can't judge it without knowing all the details

16:15 <digetx> even if they are about to make a mistake, it shouldn't be a problem to back off later on, assuming that it won't spread beyond the DRM driver

16:30 <cyndis> ugh, I'm not sure if I should update the dt-bindings yaml for nvdec to say that host1x-class is "a magic number used by host1x" or copy-paste a few paragraphs from the TRM into it

16:33 <digetx> it's not a magic number, isn't it? it encodes the hw mode programmed by CDMA stream

16:34 <digetx> mode + unit

16:34 <cyndis> i know, but i'm annoyed by the fact that we need to document the hardware in the dt-bindings, and writing those dt-bindings has already taken several times more time than the actual code patches

16:45 <digetx> cyndis: are those nvdec instances identical? if not, can't you have a different compatible name for each instance?

16:45 <cyndis> they are identical

16:45 <cyndis> it's not a problem, i'll figure out some sensible description for it

16:47 <cyndis> in some way it's an issue with DT only having one tree hierarchy, if these engines didn't have MMIO addresses then I'd imagine the host1x class would be in the reg property

16:50 <digetx> DT usually describes hw from the CPU perspective, it always becomes a problem to describe something that isn't visible to CPU

16:51 <cyndis> yep