azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing | https://github.com/azonenberg/scopehal-apps | Logs: https://libera.irclog.whitequark.org/scopehal
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<_whitenotifier-1> [scopehal] azonenberg pushed 1 commit to master [+0/-0/±5] https://github.com/azonenberg/scopehal/compare/947704982d05...9d88ad77318b
<_whitenotifier-1> [scopehal] azonenberg 9d88ad7 - Added explit "use display locale" vs "use serialization locale" argument to Unit string conversions. FilterParameter now uses correct locale for display while keeping "C" locale for serialization. Fixes #401.
<_whitenotifier-1> [scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±1] https://github.com/azonenberg/scopehal-apps/compare/dd2c179df191...c50ba6bc4b14
<_whitenotifier-1> [scopehal-apps] azonenberg c50ba6b - Fixed locale issues around file serialization. Allow use of comma as decimal separator in Unit::ParseString() if current locale uses it for that purpose. Fixes #401.
<_whitenotifier-1> [scopehal-apps] azonenberg closed issue #401: Locales with commas as decimal separator break unit parsing - https://github.com/azonenberg/scopehal-apps/issues/401
<azonenberg> but bedtime
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<Degi> bvernoux: It might be possible to build a diode based sampling gate with a few GHz bandwidth with relatively cheap components, only problem is how to make a delay to trigger the sample gate and how to trigger the input signal. For the delay I think a fast rising RC filter + comparator could work and for the trigger maybe something like a SR latch set by the clock and reset by the trigger signal, then a RC circuit integrates
<Degi> the time it was on and an ADC reads it out.
<bvernoux> Yes at least to have something good enough to do some eye diagram and basic signal integrity up to 5Gbps or 10Gbps
<bvernoux> It will be interesting to have a teardown of https://www.totalphase.com/products/advanced-cable-tester-v2
<bvernoux> They sell it 15KUSD and I'm pretty sure they use clever trick with some big FPGA
<bvernoux> So maybe that will probably cost less than 1KUSD in HW
<miek> bvernoux: https://youtu.be/u6lx1ntNoxE?t=152 has a basic teardown
<bvernoux> ha yes nice
<bvernoux> woo it is empty ;)
<bvernoux> Very fun they have masked a chipset with some SerDes lines ;)
<bvernoux> I'm pretty sure it is a cheap ASIC doing the ultra high speed stuff
<miek> the blue PCB in there looks like it might be some off the shelf SBC or FPGA board? i don't quite recognise it though
<bvernoux> Will be nice to have a detailed teardown with hi-res pictures of each boards top/bottom ;)
<bvernoux> Yes Blue PCB shall be FPGA
<bvernoux> Anyway TotalPhase have made an amazing software for the integrity from a web page
<bvernoux> It looke like a bit like ibom plugin for KiCad but for Integrity test so very nice
<tnt> if it's their custom asic why erase the marking off it ?
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<bvernoux> tnt, I suspect it is not something custom
<bvernoux> tnt, something like common controler for SSD or other with lot of SerDes for high speed transfer ...
<bvernoux> else like you say why to hide something no one could buy/use ;)
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