<AlexandrosLiarok>
any tips on profiling stm32 projects?
<Darius>
AlexandrosLiarok: Orbuculum? :)
<Darius>
depends what MCU and what tooling you have
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<bartmassey[m]>
Henk jamesmunns adamgreig tamme and anyone else who is interested in participating: the MB2 Discovery Book sprint will start in a few hours October 26, 17:00-21:00 CEST, 15:00-19:00 UTC, 8:00AM-12:00PM PST. Please meet here and we will organize and make a plan to produce a new chapter or two. The focus this time is on interrupts DMA and PWM as time permits.
<bartmassey[m]>
I look forward to writing with you folks!
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<ivmarkov[m]>
<thejpster[m]> "Ugh, Long File Names are messy..." <- The whole fs is not async. Does that mean that the impl busyloops when hitting flash and thus delays all other tasks in the same executor, or is it so fast, that this is barely noticeable?
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<thejpster[m]>
There’s a PR to make it async but it hasn’t been merged. The delays reading and writing blocks will be perhaps milliseconds long so you will definitely notice them.
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<GuineaWheek[m]>
i'm trying to use the dwt cycle counter to do some performance measurements but the compiler keeps eliding one of the reads so i get inaccurate measurements
<GuineaWheek[m]>
any idea on how to get rust to.... not do this?
<JamesMunns[m]>
If you change all the orderings to AcqRel does it change?
<JamesMunns[m]>
I think you might want Acquire ordering really, but I always have to look up which one to use in which situation :D
<JamesMunns[m]>
the other question is whether you have DWT running, I know it requires the debugger to be attached (and maybe some manual init?) for it to actually return valid values
<JamesMunns[m]>
like - is dwt just always returning zero
<JamesMunns[m]>
generally volatile operations can NEVER be reordered relative to each other, but they could be reordered across your non-volatile code (e.g. the micromath ops)
<JamesMunns[m]>
but I think if you have the fences right then it shouldn't
<GuineaWheek[m]>
DWT is running, it returns correct values
<JamesMunns[m]>
I can't remember if black_box is stable these days
<GuineaWheek[m]>
i can see it returning correct values in the debugger
<GuineaWheek[m]>
i've tried black_box, every single combination of Ordering, and still no dice
<JamesMunns[m]>
you can wrap your micromath call in core::hint::black_box(micromath::F32(theta).sin_cos());
<JamesMunns[m]>
is the compiler just optimizing the operation away entirely?
<GuineaWheek[m]>
so either start gets optimized away
<GuineaWheek[m]>
or if i use asm!
<GuineaWheek[m]>
start and end get put adjacent to each other
<JamesMunns[m]>
when you say "optimized away", do you mean you just can't print it in the debugger?
<GuineaWheek[m]>
so the dwt difference ends up being 1 cycle
<GuineaWheek[m]>
no
<GuineaWheek[m]>
there's no asm operation
<GuineaWheek[m]>
no second read
<JamesMunns[m]>
gotcha! are you looking with objdump or cargo-show-asm?
<GuineaWheek[m]>
you can see the adjacent LDRs reading from the same value
<GuineaWheek[m]>
sorry, address
<GuineaWheek[m]>
lemme try Release
<JamesMunns[m]>
you could use a real fence instead of compiler_fence, which shouldn't be necessary, but will emit dmb instructions that might make the sequencing more clear in the asm
<GuineaWheek[m]>
yeah release still emits adjacent reads
<JamesMunns[m]>
I think you need both to establish the relationship between the fences
<JamesMunns[m]>
ah, maybe that's backwards, again I use AcqRel as a default because I always have to re-think orderings out, and my gut always seems wrong :D
<GuineaWheek[m]>
other way it seems i could solve this is writing start to a static which seems to force the compiler to consider the possibility that there's an intervening access elsewhere...which seems Cursed
<JamesMunns[m]>
like, "nothing before getting the dwt is moved after it, and nothing after it is moved before it"
<JamesMunns[m]>
(in both places you acquire it)
<JamesMunns[m]>
making them all the same ordering like in your code snippet will only prevent the reorderings in one direction, I think?
<GuineaWheek[m]>
i think the ordering is correct but the fundamental problem is that the micromath operation is reorderable relative to the dwt fetches
<GuineaWheek[m]>
becaus ei think the dwt fetches are correct relative to each other but the compiler thinks that the micromath calls don't affect DWT
<JamesMunns[m]>
as I understand it, that should not happen if the orderings are right, but if you try my code and tell me I'm wrong then I can't really argue with that :)
<GuineaWheek[m]>
i tried it without black_box and it reorders
<dirbaio[m]>
I think if nonvolatile_op2 is just math on registers it can still get reordered
<GuineaWheek[m]>
dirbaio[m]: yeha it's likely math on registers because micromath doesn't use LUTs for sin/cos
<dirbaio[m]>
it's only the visible effects on memory that are guaranteed to be ordered
<GuineaWheek[m]>
DWT (or perhaps hardware timers in general) is in a spot where like, the very number of cycles executed affects what it can read
<GuineaWheek[m]>
so like, how do you even guarantee the desired behavior if you never touch memory?
<dirbaio[m]>
with something stronger than fences 🤷
<dirbaio[m]>
black_box, inline_asm
<JamesMunns[m]>
<dirbaio[m]> "it's only the visible effects..." <- ahhh, you're saying it catches with the DMA because the op is observable because we use the ptr of the buf?
<dirbaio[m]>
no, because they are memory accesses
<dirbaio[m]>
what fences do is "these memory accesses should happen before these other memory accesses"
<dirbaio[m]>
s/should/must/
<dirbaio[m]>
which is exactly what you want for DMA: the memory accesses for filling the buff must happen before the memory access that starts DMA
<dirbaio[m]>
but if you're doing just math on registers... that's not a memory access. it's not visible from outside the core, so the compiler is still free to reorder it
<GuineaWheek[m]>
i'm...still having reorderings with black_box on a different piece of code and i have Zero Idea Why
<GuineaWheek[m]>
now my dwt memory access is getting inserted in the Middle of the Code I Want To Benchmark
<GuineaWheek[m]>
the only consistent way I can seem to stop this is to write start to a static variable
<GuineaWheek[m]>
my guess is it's because it forces start to get written to memory and not just a register
<JamesMunns[m]>
writing to a static means that the "visibility" of the write is a much huger scope
<JamesMunns[m]>
like, other threads could theoretically access it, it's not local to the current execution context
<JamesMunns[m]>
which I assume makes the optimizer much more pessimistic
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<thejpster[m]>
<JamesMunns[m]> "(I don't remember seeing the "..." <- BCC is a conditional branch where the condition is Carry Clear IIRC.
<JamesMunns[m]>
yeah
<JamesMunns[m]>
I did look it up, it just didn't ring a bell :)
<thejpster[m]>
Not so Reduced these days.
<thejpster[m]>
More like Reduced Addressing Mode Instruction Set really.
<JamesMunns[m]>
"everything but the MMU architecture"
<AlexandrosLiarok>
<Darius> "depends what MCU and what..." <- stm32h745 and I am flexible enough to pick whatever I need as long I can get a better workflow
<AlexandrosLiarok>
I think native profiling is something that I've been missing a lot
<AlexandrosLiarok>
I do have a VST emulator but that's not the same especially due to fpu capabilities
<AlexandrosLiarok>
orbuculum seems nice
<Darius>
I've only played with it a little with a blackmagic probe but it is pretty neat
<Darius>
using an orbtrace would give more bandwidth though
<bartmassey[m]>
Henk jamesmunns adamgreig tamme and anyone else who is interested in participating: the MD2 Discovery Book sprint starts now. Please say "hi" if you're participating…
<adamgreig[m]>
hi!
<JamesMunns[m]>
Ah! I did not put it in my calendar and am afk for a bit, but can join later!
<bartmassey[m]>
adamgreig: Shall we set up a temp channel for this?
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<tamme[m]>
hi
<bartmassey[m]>
James Munns: No problem. Join us when you can
<adamgreig[m]>
personally i don't mind here or a new channel
<bartmassey[m]>
tamme: Welcome!
<bartmassey[m]>
Ok, here is fine. We'll probably only be here for a few minutes anyhow.
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<AlexandrosLiarok>
<norineko> "Alexandros Liarokapis: the h7..." <- I have, haven't had much lack so far although the arbuculum folks are helpful.
<AlexandrosLiarok>
> <@libera_norineko:catircservices.org> Alexandros Liarokapis: the h7 has a few quirks but if you go to the 1bitsquared discord #orbuculum channel you'll find folks who've done it.
<AlexandrosLiarok>
* I have, haven't had much lack so far although the arbuculum folks were very helpful.
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<bartmassey[m]>
Henk jamesmunns adamgreig tamme : The text we wrote so far for Book Sprint is in https://github.com/rust-embedded/discovery-mb2 in the branch `sprint-20241026'. Let's handle further edits and updates as PRs to that branch rather than dumping it in the HackMD (https://hackmd.io/zcqqCWvVRrqdhLOCzWLakg)? That will help me keep track of what's changing as I edit…
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<AlexandrosLiarok>
any idea where I can get proper SVDs for the cortex-m registers/
<rmsyn[m]>
aliarokapis: there is the `rust-embedded/cortex-m` repo that has register definitions. I wasn't able to find SVDs with register definitions, however I wrote a tool for parsing DTS files, and producing a SVD. If you want help taking register info, and adding it to the known definitions in that tool, you could generate your own SVD. here is a link to the tool: https://codeberg.org/weathered-steel/svd-generator
<rmsyn[m]>
it will be a bit of upfront manual work doing the translation, though. so, if others know of vendor supplied SVD files, maybe that would be better
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<M9names[m]>
github has a search function. it lets you filter not only on text, but on file type too.
<M9names[m]>
i suspect you'll be able to find what you're looking for if you specify a register name and a file type like xml or svd, as below:
<M9names[m]>
<berkus[m]> "https://www.arm.com/company they..." <- this is kinda the problem though. if you rely on how the company stylises itself you will be wrong again in a few years when they change their mind again.
<berkus[m]>
We can call them LEG or "A company that shall not be named"
<M9names[m]>
Love the wikipedia entry: ARM (stylised in lowercase as arm) and run by Arm Holdings.
<M9names[m]>
So i guess ARM when referring to the chips, arm when in logo form, and Arm when talking about the company.
<berkus[m]>
M9names[m]: > <@9names:matrix.org> Love the wikipedia entry: ARM (stylised in lowercase as arm) and run by Arm Holdings.
<berkus[m]>
> So i guess ARM when referring to the chips, arm when in logo form, and Arm when talking about the company.