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<re_irc> <> is there a good chat room for general embedded development, not Rust specific?
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<re_irc> <> Question for folks with RISC-V experience. I am using a SiFive Unmatched (U74-MC).
<re_irc> <> I have `MSEL` set to 0b0_0000 and `gdb` is showing my program is loaded into L2-LIM.
<re_irc> <> I can single-step through instructions just fine, until I hit a `csrw` statement. `csrr` works fine. I believe I am in Machine mode on the S7 Monitor core. Any ideas what I could have missed?
<re_irc> <> Minimal reproducible example:
<re_irc> <> Was writing to an S-register on a core without S-mode.
<re_irc> <> Any of you familiar with the stm32f446?
<re_irc> <> I was going to buy a couple since it’s like the only stm32f4 available, but it seems like stm32-rs doesn’t support it
<re_irc> <> Actually nevermind, turns out I can’t read
<re_irc> <> Doesn’t support sdio :(
<re_irc> <> there are definitely f446's that support SDIO, is it just the one you've found that doesn't?
<re_irc> <> 9names: Well, it’s actually just the hal doesn’t enable the sdio feature for that series it seems
<re_irc> <> The data sheet definitely has sdio
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<re_irc> <> Does anyone have an example of linkers + preinit of using and initializing the RAM2 block of an STM32 for statics using #[link_section]? specifically the bss part in a correct and sound way?
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<re_irc> <> Lachlan Sneff: If I recall correctly: When I wrote the sdio driver, looking at the SVD for the F446, it didn't match the other F-series SVDs. So I wasn't sure it had the same controller.
<re_irc> <> Not sure I've seen this. cortex-m-rt doesn't have any way to initialise multiple sections and we determined it probably must be done in assembly.... one possibility that comes to mind is using a custom linker script (just copy link.x to your project directory) and changing sdata and edata to cover your new section, but then all statics will go there
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<re_irc> <> adamgreig: Hmm.. What i have now is basically
<re_irc> <> MEMORY
<re_irc> <> FIRMWARE : ORIGIN = 0x08004000, LENGTH = 480K
<re_irc> <> {
<re_irc> <> Then i am using it with `#[link_section = ".ram2"]`
<re_irc> <> oh, sorry, I thought you wanted to initialise data
<re_irc> <> No, just zero initialize
<re_irc> <> zero-init is somewhat simpler
<re_irc> <> what you're doing unfortunately falls into this annoying rust memory model problem where it's not technically allowed to use rust code to create pointers from nothing that point to existing statics and then turn them into &mut references, because it means there's mutable aliasing going on
<re_irc> <> which is why the r0 crate is deprecated, as it stands there's no way to do it soundly in rust (probably)
<re_irc> <> although, uh
<re_irc> <> is this in a bootloader distinct from the actual application, or are they linked together?
<re_irc> <> That is in a destinct bootloader, seperate binary
<re_irc> <> unusually, if the rust paplication with this code in it doesn't actually itself have any statics in RAM2, then it would completely bypass the problem, lol
<re_irc> <> well that's convenient
<re_irc> <> assuming it doesn't have any statics placed in ram2
<re_irc> <> bootloader doesn't use ram2 at all
<re_irc> <> that should work fine then
<re_irc> <> you could inline the four lines of code from r0 that you're using and save having it as a dependency if you wanted, this part isn't complicated
<re_irc> <> but yea, the only reason it's a problem is initialising statics that are accessible to the same program (which is usually always the case, for initialising the normal bss), but not an issue here
<re_irc> <> Alright, that sounds good..
<re_irc> <> It also seems to work great, only reason im questioning it, is that im seing what appears to be random system resets that i cannot figure out where is coming from. I have ruled out panics and stack overflows, i am currently investigating if it could be BOR based.. Are there any other reasons an STM32 would suddenly reset after having run some code for days, that i need to investigate?
<re_irc> <> ugh, that's annoying to debug
<re_irc> <> i have just wrote up a patch to check RCC_CSR flags for a reset reason, just waiting for it to happen again :( Can't seem to find a way to force a replication
<re_irc> <> do your panic and/or hardfault handlers reset?
<re_irc> <> Both do, but i am using panic_persist, and that one is empty on following reboot. I am also using flip_link, and yet hardfault is never hit
<re_irc> <> if you can, leaving it hooked up to a debugger with a breakpoint set on panic, hardfault, and reset, so it will at least stop the moment it resets, might be instructive
<re_irc> <> I have tried that, but i have not been lucky enough to replicate it with a debugger in yet. Not that don't think it will happen, just that it is kinda rare.. Super annoying!
<re_irc> <> UB stuff of any kind wouldn't result in a system reset, would it?
<re_irc> <> eg `.._unchecked()` calls, or reading uninit memory, etc?
<re_irc> <> _unchecked and the like will call the panic handler
<re_irc> <> Okay, so that should be covered
<re_irc> <> reading uninit memory will just work I expect
<re_irc> <> doing anything that the cpu core doesn't allow (reading invalid memory address etc) causes a fault, by default all faults escalate to hardfault unless you've installed memfault etc handlers
<re_irc> <> It escalates to hardfault? i though it would call the DefaultHandler in cortex-m-rt? Isn't that an empty loop?
<re_irc> <> no, all interrupts and exceptions except hardfault default to defaulthandler, but hardfault has its own default for some reason (either can be overridden by the user)
<re_irc> <> hardfault does default to an infinite loop, though
<re_irc> <> Yeah, i have kinda hacked a solution for hardfault handling that seems to work, as all cases should result in system reset anyways i don't really care i i break my stack.
<re_irc> <> ```rust
<re_irc> <> #[naked]
<re_irc> <> #[no_mangle]
<re_irc> <> in that specific case it might make more sense to set that as BusFault which should catch any out-of-bounds memory access like a stack overflow when using flip-lld, and then you can have a separate panic message for hardfault
<re_irc> <> Huh, cool! I didn't know flip-link was actually causing a BusFault, being escalated to a HardFault.. TIL
<re_irc> <> you'd also need to call `scb.enable(Exception::BusFault)` to have it used instead of hardfault, iirc
<re_irc> <> Thanks 👍️ Will give it a shot
<re_irc> <> I doubt it's what you're hitting now though, since it would already turn into a hardfault -> into a panic
<re_irc> <> (annoyingly I think panicking inside hardfault is often not OK though, because it can cause re-entrancy to your panic handler, which is likely not thread safe)
<re_irc> <> Which is why i move my MSP first
<re_irc> <> (at one point we had c-m-rt default to panic in those handlers because it seemed like a really nice way to handle it, but because a hardfault can pre-empt a panic, it isn't in general sound)
<re_irc> <> sure, that helps avoid stack overflow related problems in the panic handler, and maybe for your panic handler it's enough
<re_irc> <> Ah , in the non overflow hardfault cases?
<re_irc> <> in principle a panic handler might be like, sending something out UART, or writing to some reserved RAM for panic-persist, or anything like that
<re_irc> <> ```rust
<re_irc> <> #[naked]
<re_irc> <> So this should be valid in my case, assuming i enable the busfault exception?
<re_irc> <> #[no_mangle]
<re_irc> <> I'd keep the link_section tags to ensure RealBusFault is placed nearby to BusFault in flash, otherwise the difference could end up outside the range of the branch instruction
<re_irc> <> I'm not sure if you can use the normal #[exception] macro here too but I guess there's no need
<re_irc> <> anyway it should be pretty easy to test that it's working, just read an invalid pointer somewhere
<re_irc> <> (alas not 0x0 because that's valid 🙃)
<re_irc> <> i am just getting `no memory region specified for section '.BusFault.user`?
<re_irc> <> Is it called something else?
<re_irc> <> stick it in hardfault
<re_irc> <> there's no region specified for BusFault because it wouldn't in general be needed
<re_irc> <> ahh, okay
<re_irc> <> the reason it's in the linker file for hardfault is because the real hardfault handler (HardFaultTrampoline) is defined in assembly and uses `b HardFault`, so HardFault needs to be placed close-by
<re_irc> <> That makes sense 👍️
<re_irc> <> One other quick question.. Reading out the SCB_CSR reset reason flags, it seems like the `PINRSTF` is always set, even if i just do an `SCB::sys_reset()`.. Anyone who can tell me why that is the case? I read it, and then set the `RMVF` bit afterwards to clear the flags
<re_irc> <> could your debugger be asserting nrst?
<re_irc> <> Hmm.. Not sure, give me 1 minute and i'll try without debugget
<re_irc> <> I'm not sure how it tells because iirc the nrst pin gets driven for anything, but maybe that's why this is a "simplified" diagram
<re_irc> <> even without a debugger attached, a sys_reset call results in both `PINRSTF` and `SFTRSTF` asserted..
<re_irc> <> maybe it really is how the diagram looks (this is for an f4 in particular but I think it's widespread) and the software reset (via `sys_reset()`) drives nRST low for 20µs so is detected as a PINRSTF too
<re_irc> <> I can't say for sure
<re_irc> <> Hmm.. That might make sense.. A bit strange though, but it would explain it
<re_irc> <> maybe BORRSTF wouldn't generate PINRSTF? could try undervolting it til BOR kicks in
<re_irc> <> though it's a pain and probably not that informative
<re_irc> <> I checked with `IWDGRSTF` and that asserted all 3.. (the `SFTRSTF` in that case was probably caused by the way my bootloader works, as it always does a sys_reset())
<re_irc> <> Damn.. I just OTA'ed this to my devices that has been restarting sporadically, and the `BORRSTF` bit is set :(
<re_irc> <> Any suggestions to debugging BOR issues?
<re_irc> <> That might be a good clue at least! Perhaps you can put a scope on vcc and set the trigger point to the BOR level and check it's happening or getting close... what hardware is it? Perhaps not enough decoupling or too high pdn inductance or... anything like that
<re_irc> <> its an STM32L475VGT
<re_irc> <> I guess the scope trigger would be a good start, just to confirm
<re_irc> <> Maybe you can disable brownout detection and see what happens instead lol
<re_irc> <> I mean, is it on a custom PCB that conceivably could have power supply issues?
<re_irc> <> I don't think it's possible to disable? "The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled
<re_irc> <> with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except
<re_irc> <> Shutdown mode, and cannot be disabled."
<re_irc> <> adamgreig: Yeah, it is :(
<re_irc> <> the option bytes have a BOR_LEVEL that configures the voltage where BOR trips, but I think the default is the lowest at 1.7V
<re_irc> <> exactly :/
<re_irc> <> what vcc are you at?
<re_irc> <> 3.3
<re_irc> <> Soo its a long drop to 1.7..
<re_irc> <> I do have a 4G modem on the same supply though, so im thinking if the sporadic power draw from that one might cause voltage drops
<re_irc> <> yea....
<re_irc> <> oh, yea, definitely a possible culprit, those things can draw multiple amps on tx
<re_irc> <> maybe a good place to start measuring anyway, or looking to see if tx activity correlates with resets
<cr1901> adamgreig: I won't be here for the meeting today. Like last week. But this time I remembered to tell you :P
<re_irc> <> no worries! I actually forgot it's a tuesday since we had a national holiday yesterday, lol
<re_irc> <> If I take and unwrap peripherals inside the main function, but my interrupts are outside of main, how do I access registers to reset them, like the ISFR?
<re_irc> <> Hey I'm still wondering why RTT isn't working randomly for me, and have a question: is [this]( a race condition? What happens if `primask` is changed between it being read and interrupts being disabled?
<re_irc> <> Also I don't know enough about ARM arch to say whether primask_r and cpsid interact.
<re_irc> <> cpsid/cpsie do set/clear primask
<re_irc> <> the purpose of that primask read is to allow nested critical sections: the inner one doesn't have to reenable interrupts, because they were already disabled. if it does, it'd break the outer one
<Lumpio-> If interrupts were disabled when entering that function there's no race condition
<re_irc> <> it's never a race
<Lumpio-> What if there's an interrupt after primask read and cpsid *and* the interrupt disables interrupts
<re_irc> <> yes, an interrupt can happen between `register::primask::read();` and `interrupt::disable();`
<Lumpio-> That's the only race I can think of
<re_irc> <> and that interrupt handler might have a critical section too, yup
<Lumpio-> I mean between primask read and cpsid
<re_irc> <> but it's supposed to "end" within the handler
<Lumpio-> I don't mean a critical section
<Lumpio-> What if the interrupt handler calls interrupt::disable()
<re_irc> <> so the handler is supposed to leave PRIMASK as it was before
<Lumpio-> Nesting these critical sections works fine yes
<Lumpio-> Who says the handler must do that
<Lumpio-> It's probably a very weird thing to do, but is it a race still
<re_irc> <> ah yeah, then the CS wouldn't see that and would reenable it
<re_irc> <> PRIMASK is only supposed to be used for critical sections though..
<re_irc> <> i'd argue doing a stray `interrupt::disable()` like that is wrong
<re_irc> <> I don't think the architecture has a way to "set PRIMASK and get the old value atomically" at all...
<re_irc> <> so this is the way you do it
<re_irc> <> `cortex_m::interrupt::free()` does exactly the same:
<re_irc> <> The error that I'm trying to debug is that rtt (with defmt-rtt and probe-rs-rtt) randomly stops working after a large number of SPI writes using easy-dma on nrf (using embassy)
<re_irc> <> The number of writes required is always different but similar (in the range 400-420)
<re_irc> <> what probe are you using?
<re_irc> <> It's a very wierd problem, as all race conditions are :(
<re_irc> <> I'm using the nrf52 discover/evaluation board
<re_irc> <> I've ordered one of the new probe-rs ones, looking forward to seeing if that fixes the problem/proves it is a probe problem
<re_irc> <> nrf52-dk? so nrf52832+jlink?
<re_irc> <> nrf52-dk
<re_irc> <> it just feels like it isn't going to be a probe problem though, because it is unrelated to the number of rtt writes - the problem occurs even if I don't write anything during the spi loop (it doesn't work after)
<re_irc> <> strange
<re_irc> <> Because I'm using embassy, other things happen during the DMA write - that's where there could (in theory) be a race between it and the rtt
<re_irc> <> IKR!
<re_irc> <> I hate these kinds of bugs
<re_irc> <> and you know 100% sure the program keeps running? it's just that you stop seeing logs?
<re_irc> <> Yeah, I've put some code in to write to a screen peripheral, and it continues to change after the rtt stops
<re_irc> <> (which means the executor is definitely still working)
<re_irc> <> It also responds to some input (a button I press)
<re_irc> <> could the core be rebooting? defmt gets angry if it reboots
<re_irc> <> hmm, can I trap/record that somehow?
<re_irc> <> dunno, flash some led or something at start of main()
<re_irc> <> ok good idea I can do that
<re_irc> <> defmt has no framing, so if the core reboots in the middle of writing some message, it can corrupt the stream
<re_irc> <> and probe-run doesn't catch that
<re_irc> <> hmm
<re_irc> <> it's worth a look, I will report back
<re_irc> <> and the stream can sometimes corrupt in a way that makes the defmt decode think it's a loooooooong message, so it never finishes reading it so that it looks like it "stops"
<re_irc> <> something to try too is to patch probe-run to print whether there are still bytes coming from RTT or not
<re_irc> <> to check if that's the case
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<re_irc> <> jamesmunns: QQ: in postcard, when deserializing a struct that contains enums, is there a way to get a different Error for each field, in order to know which field failed deserialization? e.g. if an u8 in a packet is out of the valid ranges, I want to know that it was that field and log it with defmt
<re_irc> <> IIRC, error handling in postcard is pretty minimal (read: bad) at the moment. If you can find a way to change postcard to get that kind of info out, I am very open to PRs!
<re_irc> <> I don't THINK today that is possible, but likely because I've never tried :)
<re_irc> <> sure, will explore! just wanted to see if there was already a way
<re_irc> <> for enums, you are going to need to look at the varint (read: variable sized integer) code, which is what I use to encode the enum variant
<re_irc> <> Then we give that varint, changed to a u32, to serde, to pick the right variant.
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<re_irc> <> (thinking about this a bit more): this might actually be a bigger serde question
<re_irc> <> They have the `expected` field, but that prints a runtime generated debug string
<re_irc> <> so in serde there are visitors, and you can print errors out from the visitor
<re_irc> <> yeah
<re_irc> <> so for embedded and defmt, not great, as far as I can tell
<re_irc> <> Yeah, that makes sense, I'm not sure how to get something like ` failed, because negative`
<re_irc> <> can't you return your own error type? then inspect directly or impl defmt::Format for it or whatever
<re_irc> <> Yeah, I could probably error out with "failed in a u8 visitor"
<re_irc> <> but maybe not which field (which isn't available in the visitor or deserializer, afaik)
<re_irc> <> even in the more stringy serdes, like json, I don't think the FIELD knows the KEY it is associated with
<re_irc> <> it just knows "oh, this key is going to visit this kind of struct"
<re_irc> <> and even then, by the time you get to the visitor, you're working with primitives
<re_irc> <> BUT! That doesn't mean it's not possible. Just that I have no idea how :D
<re_irc> <> you could (maybe) get the INDEX of the input that caused it to fail?
<re_irc> <> then dump the whole message over defmt, for post-analysis?
<re_irc> <> not sure if that is reasonable/helpful though
<re_irc> <> definitely better than nothing!
<re_irc> <> Right now, postcard usually just sub-slices the input to smaller and smaller parts, taking bytes/slices at a time
<re_irc> <> (`take_byte` and `take_n` or something like that in the code)
<re_irc> <> that could probably figure out the offset from (original size - current size)
<re_irc> <> But yeah, that's the only thing I could think of, atm
<re_irc> <> lemme know if you find a better way!
<re_irc> <> room meeting time again! agenda's at, please add any announcements or topics you'd like to discuss, and we'll start in 5min :)
<re_irc> <> I've nailed the micro:bit magnetometer stuff down to it not being properly calibrated for where I am (when I calibrate it with the micropython stuff from the BCC the heading angle is like 40 degree off...)
<re_irc> <> And a person who goes by caemor made an PR + issue on the discovery book rewrite so its not only me working on it now \o/
<re_irc> <> nice o/
<re_irc> <> magnetometers huh
<re_irc> <> im gonna keep my distance from them after this if i can
<re_irc> <> just use loads of gps receivers 🙃
<re_irc> <> ublox have a 'heading-only' slightly cheaper receiver now that does dGPS RTK to your main receiver just to work out heading
<re_irc> <> you just wire their serial ports together and it spits out heading, kinda cute. also like 50x the price of a magnetometer, so...
<re_irc> <> I considered for a moment to do the calibration procedure as described by STM but thats 3 pages of MATLAB vs like 400 lines of C++ from the microbit I hope STM will forgive me for the betrayl
<re_irc> <> heh
<re_irc> <> ok, let's get started! I couldn't think of any announcements from the last week, does anyone have anything?
<re_irc> <> well, shout later if you think of any, next up is just a quick revisit of the discovery book rewrite, I think we basically covered everything we needed to last week, was there anything else to discuss hargonix?
<re_irc> <> adamgreig: What's the plan for the newsletter?
<re_irc> <> Nope, I'm just gonna try to get this calibration thingy going this week and then the last chapter should be ready to merge and we can proceed as discussed
<re_irc> <> oh, good reminder therealprof, I'll stick that on the agenda
<re_irc> <> ok, next up is embedded-hal, quick note that the PR to flip the module structure inside out is now merged (
<re_irc> <> any other PRs that warrant some further discussion, eldruin / therealprof ?
<re_irc> <> What are the blockers for merging the async traits?
<re_irc> <> Not from my side. Was only on review duty last week. 😛
<re_irc> <> as in ?
<re_irc> <> eyah
<re_irc> <> AIUI it's having 2 HAL impls?
<re_irc> <> we can discuss
<re_irc> <> if so, if I impl them in embassy-nrf and embassy-stm32, would that count? :)
<re_irc> <> sure
<re_irc> <> not sure if that should count as 1.5 or something haha
<re_irc> <> someone needs to write another async hal
<re_irc> <> i'd have thought the important thing is it's two totally different mcu peripherals
<re_irc> <> drivers using the async traits would also be needed
<re_irc> <> I guess also embassy for that :P
<re_irc> <> fwiw, drogue-tls and drogue-device have drivers that will migrate to these traits when merged
<re_irc> <> Are we fine with promoting things which only work on unstable and might have to change if unforeseeable stabilisation problems show up?
<re_irc> <> they have to be behind a feature gate anyway due to being nightly, it seems like on balance better to have something in e-h that people can start using and getting experience with?
<re_irc> <> since it has to be feature gated it's should be ok to make it clear it may have to change if rust stabilises something else, right?
<re_irc> <> as long as its behind some feature flag, I think it's ok, and that we should be open to change them based on feedback
<re_irc> <> Well, I guess there're two questions in there.
<re_irc> <> it seems like both driver writers and hal writers want to see async traits in e-h asap because it will be immediately and practically useful, and they seem to be on the way to stabilisation in rust now too
<re_irc> <> One is about promoting unstable. The other was: how confident are we that the features stabilise as-is and don't require later changes.
<re_irc> <> my read on the rustc side of things is that they don't expect any serious changes and hope to get more and more GAT-related stuff stable soon? I'm not fully plugged in to that though, so I might be mistaken
<re_irc> <> thats my impression as well, but it's hard to predict the future
<re_irc> <> I would rather hope that we can finally wrap up e-h and ship it rather sooner than later.
<re_irc> <> Having a very rudimentary understanding of the async ecosystem - is it feasible to implement async e-h traits without GATs?
<re_irc> <> nope
<re_irc> <> Not without `alloc`.
<re_irc> <> therealprof: agreed, but I don't see in principle a reason we couldn't have an async feature-gate in 1.0 that we later turn into a no-op once it's stable?
<re_irc> <> I understand the worries about the previously bad `unproven` gate, but the motivations are somewhat different here - it would already be proven, it's instead that it needs nightly
<re_irc> <> I guess it's also fair to worry about what it means to make breaking changes to something behind a nightly-only feature-gate...
<re_irc> <> I don't have a problem with the feature gate. I don't think this is like unproven at all.
<re_irc> <> yeah IMO the traits are quite proven
<re_irc> <> they mirror the existing blocking traits
<re_irc> <> I've already proposed to use `async` feature
<re_irc> <> Agreed
<re_irc> <> what was bad with the unproven gate? (sorry for distracting the conversation, just curious) All features being put there and people relying on it too soon?
<re_irc> <> I suggested if we merge it, this feature would _not_ be covered by the semver guarantees, since it is based on nightly
<re_irc> <> I think that's fair
<re_irc> <> lulf: nothing ever got proven, so it became basically required
<re_irc> <> If we want to do that though, what's the difference between just shipping it in a separate async-embedded-hal crate?
<re_irc> <> so it would just be for people that are fine with nightly shenanigans
<re_irc> <> I think I would be a lot more confident if someone could summarize which unstable features are needed and include their upstream tracking status.
<re_irc> <> it can be a separate crate too, but then why are the `nb` traits in main e-h and `async` traits separate?
<re_irc> <> just GATs
<re_irc> <> Just a single feature? What's the exact name? And what's the upstream stabilisation tracking issue?
<re_irc> <> on the implementor side you might want `type_alias_impl_trait` too if you want to impl them with `async fn` or `async{}`, but you can do without if you manually do `struct FooFuture; impl Future for FooFuture`
<re_irc> <> for *defining* the trait you just need GATs
<re_irc> <>
<re_irc> <> Can you stick the information on the issue? Then we'll call for a team decision.
<re_irc> <> lulf can you add the info about the drivers there as well?
<re_irc> <> I guess the PR needs rebasing for the inside-out modules too?
<re_irc> <> ... or PR rather. 😉
<re_irc> <> ok, shall we move on to ?
<re_irc> <> I haven't looked at the updates in the issue yet, I'm afraid.
<re_irc> <> I have two quick e-h pre-rfcs, is this a good time to mention them?
<re_irc> <> go for it
<re_irc> <> First: Require all errors to be `Debug`
<re_irc> <> Second: Blanket impls for references, for example `impl<T: OutputPin> OutputPin for &mut T`
<re_irc> <> I think the new errors in 296 also requires Debug?
<re_irc> <> adamgreig: Yeah, it looks like it does. That only covers serial, spi, and i2c though.
<re_irc> <> I think requiring `Debug` everywhere should be fine.
<re_irc> <> I will probably open PRs for both of those Eventually ™️ unless someone else does it first
<re_irc> <> I can't think of any reason it would be bad to provide impls for references, but maybe there's something sneaky...?
<re_irc> <> Currently, a HAL could impl the traits differently for `SpiStruct` vs `&mut SpiStruct`, but I'm not sure if there is any good reason to do that. A blanket impl would disallow that.
<re_irc> <> Commented on the errors PR:
<re_irc> <> > Maybe this PR should enforce that the Error associated types impl the Error trait? The original proposal does so.
<re_irc> <> I don't understand this, the PR does require the associated types to implement the `Error` traits
<re_irc> <> Has anyone bikeshedded `i2c::Error` vs `i2c::I2cError` yet?
<re_irc> <> then the traits should be `i2c::I2cWrite`
<re_irc> <> `i2c::Error` is the consistent one
<re_irc> <> we have `i2c::Write`, `spi::Write`,... so I figured `i2c::Error` would be more in line with that
<re_irc> <> how? it just adds Error/ErrorKind, but doesn't change the associated types to `type Error: Error`
<re_irc> <> ach sorry I redid the whole PR today due to inside-out and missed adding the bounds
<re_irc> <> ah OK :)
<re_irc> <> the whole point is requiring that
<re_irc> <> thanks for noticing!
<re_irc> <> This distinction depends on how you imagine users importing. For example, `i2c::Error` makes more sense if you assume the person imports mainly modules. If you assume the user imports data structures, `i2c::Error` causes conflicts. I've been going with the latter for flexibility and avoiding name confusion and collisions. Eg `dac::DacMode`, `adc::AdcChannel`, `timer::TimInterrupt` etc. Potentially...
<re_irc> ... redundant, but makes it obvious what item you're using if importing directly
<re_irc> <> You can always let the user do `use embedded_hal::i2c::Error as I2cError;`
<re_irc> <> sadly I don't think the rust api guidelines say much about it, but rust stdlib is pretty consistent in having things like `std::io::Error`, `std::fmt::Error`, etc
<re_irc> <> True. I was using that approach before switching to explicit names
<re_irc> <> I feel like i2c::I2cError is anti-DRY. I'm sure I've seen it as a convention somewhere that you should avoid including duplicate names in paths. If the module makes it clear what it is, it needs not be repeated. But that's my opinion and I will refrain from futher bikeshedding :D
<re_irc> <> ok, we're pretty much out of time so I've updated a few points on the agenda to discuss next week, though a quick reminder that the newsletter is open for anything you'd like to add and we'll probably publish the next edition in a couple of weeks :)
<re_irc> <> and that's all for this week, thanks everyone!
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<re_irc> <> know this is a few years out... but i wonder how many of us here would like to use something like this?
<re_irc> <> apparently its old tech from the 70s thats seeing a revival cause of low powered computing devices. looks like they are aiming for 5v 0.7uA based on their data sheet...
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<re_irc> <> 0.7uA average is pretty hard to hit unless you're sleeping most of the time. I could see some uses for ultra low power implantables, but anything with wireless connectivity gets a bit harder. From what I remember, they aren't very good at providing pulsed high amperage currents either (e.g. short 20mA pulse for radio usage), but I don't remember anymore