sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<drewfustini> palmer: I ran into this regression on next too: https://lore.kernel.org/all/CA+G9fYug_77HoqyonvsnJiya2q+0-hf9k4Yjk_dDn7P91Sq+3A@mail.gmail.com/ do you know if any one is looking at this issue yet?
<palmer> IIRC Alex's PR has a diff that fixes it
<drewfustini> Thanks, I saw the PR but I wasn't sure if that resolution was for this problem
<drewfustini> I see it now that I read more carefully :)
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