sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<ball> Does LoongArch count as RISC-V?
<palmer> no
<ball> Thanks
<xypron> ball: LoongArch is closer to MIPS.
<ball> Loong64 was MIPS. Heard conflicting reports about LoongArch
<palmer> ya. IIUC a lot of the SW looks similar because RISC-V was the base point for their port, but the ISA itself came straight from MIPS (ie, didn't follow the RISC-V side of the fork)
<ball> Hmmm... weird.
<palmer> I don't think it's that crazy, RISC-V makes a lot of decisions I'd un-make these days and if I had a history of MIPS already I'd seriously consider just starting from there
<ball> Is it too late for RISC-V to unmake those decisions?
<palmer> tough to tell: we'd have to completely throw away binary compatibility, but it's not like there's any binary-compatible market out there now. So I think it could be done technically, but it'd require a design team really pushing on it. The RISC-V vendors I see are generally hoping that the SW will just work itself out and they can follow, so they wouldn't make that sort of decision
<ball> Perhaps it's time for RISC-VI then.
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