sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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* ball watches the Lichee Pi 3A video...
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<jbe> mfny: yeah, the chips are different height
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<geist> question re Svnapot extension
<geist> i'm re-reading it now and I can't figure out how you're supposed to handle (aside from just not using it in this case) where you want say a 64K contig page but so happens your physical address is power of 2 aligned > 64K
<geist> it seems like that would always interpret it as a larger page (assuming the implementation supports != 64K, which it doesn't now)
<geist> it's a clever design in that it only needs one bit to handle more than one page size hypothetically, but seems like it has this detail that makes you have to not use it conditionally based on the alignment of the physical page
<geist> and that's probably the answer
<geist> but for example if you allocate 64K pages out of your PMM every 1/4 of them will be aligned to some higher power of 2...
<geist> or something thereof
<geist> ohh nevermind, i think i get it now. the ppn is actually setting the low bit one *below* the 64k boundary as a signifier
<geist> it's not super clear in the spec but once you work out the math it makes sense
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