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<seds>
I am having some problems with the compiled crosstool-ng for RISC-V. I keep getting Error: unrecognized opcode `csrw mtvec,x10' when compiling with the built gcc. Any idea what am I missing?
<seds>
I've also compiled riscv's gcc toolchain, but I got the same result
<la_mettrie>
just a guess, but makes me think if the instruction extension containing csrw is in use
<seds>
hmm, well, I am compiling this against the neorv32 soc, using their hello world example
<seds>
it should work, at least it did a few weeks ago
<seds>
I am almost sure I am missing something on the compiler though
<seds>
but then again, it is odd that two different riscv compilers gave that error
<seds>
does gcc have any flags which outputs all the available opcodes?
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<sorear>
maybe related to the change recently to have rv32i no longer imply zicsr
<sorear>
are you using march options?
<sorear>
does tacking _zicsr on the end help?
<sorear>
"available [mnemonics]" is a gas thing, not a gcc thing, and I'm not aware of any such flag, sorry
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<seds>
can you share the commit that no longer implies zicsr?
<seds>
nevermind, found it
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* coolbeans
waves
<coolbeans>
oi, the community is growing indeed
<coolbeans>
i haven't poked around here since hifive1 came out and i swoop'd a preorder
<coolbeans>
my email got notification of some MangoPi-Nezha MQ in the pipeline... oi!
<coolbeans>
pretty coolbeans to see such a benchmark
<coolbeans>
what else is going on in the world of riscv
<coolbeans>
anyone have a decent 64 out?
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<la_mettrie>
what is decent...
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<coolbeans>
la_mettrie: boots to an operating system
<coolbeans>
i guess i didn't just mean a 64 chip, but a 64 board
<coolbeans>
any riscv64 boards out there that can run a terminal?
<qwestion>
How do I follow libre toolchain developments , like, to design socs
<qwestion>
Or cores at least
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<la_mettrie>
qwestion: gcc and other parts of the toolchain probably have their own e-mailing lists and channels
<la_mettrie>
and hubs
<la_mettrie>
*gits
<qwestion>
GCC to design cores/socs? Reread my q
<muurkha>
don't be rude to people just because they misunderstand you
<la_mettrie>
ok, i usually think of software when somebody says toolchain
<qwestion>
I've heard of betrusted using FPGA tools like yosys and co and that also isn't the toolchain I'm looking for...
<qwestion>
muurkha: how can I word it less rude?
<[exa]>
"libre toolchain developments" is literally a question for gcc mailing list :]
<[exa]>
designing socs is I'd say a completely different problem, though related
<muurkha>
[exa]: there's also a libre toolchain for designing socs (the yosys and co menttioned above)
<muurkha>
qwestion: I read "reread my q" as being pretty rude; you could've said "I didn't mean that" or at greater length "I'm talking about HDL toolchains for synthesis and place & route"
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<muurkha>
what's obvious to one person often isn't obvious to another
<[exa]>
ah these toolchains.
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<qwestion>
Got it, I'm on mobile and sometimes choose efficiency over unambiguous politeness
<sorear>
we get mentioned somewhere?
<qwestion>
?
<qwestion>
I think I will ask these (Free/Libre toolchain (Yosys/Trellis/Nextpnr)) projects as well as Ariana and alibaba's subsidiary's forum
<qwestion>
2nd RISC-V Week: 3rd RISC-V Meeting + OpenHW Day Two RISC-V events over 3 days! The program is online and registration is open! ... CPU, on top of Lattice ECP5 FPGAs programmable using a Free/Libre toolchain (Yosys/Trellis/Nextpnr)
<sorear>
looks like a spike in new users on the channel, wondering if that was prompted by anything
<qwestion>
I've been following for a while, but maybe fosdem?
<qwestion>
They had open-hardware devrokom on matrix
<qwestion>
Devroom
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