klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
<geist> zen 4 guide? i ust googled for it, first hit
<geist> zen 4 optimization guide
<mjg> so i'm gonna see about doing a full build
<mjg> but it is going to take quite some time
<heat> geist, yeah found it, thanks
<geist> ah interesting, the reason gcc did your code efore where it used rip relative into a register, then tested it, then conditionally branched may be because:
<heat> it agrees with the intel manual and says that for cmp/alu + branch the flag-writing instruction may not use rip-relative addressing to get fused
<geist> for instruction fusion to happen: "• The flag writing instruction cannot use rIP relative memory addressing."
<geist> ie, the `cmpl 0, 0[rip]` style thing clang did is a bad instruction
<heat> yes, intel said the same thing
<heat> yep, clang is wrong there
<moon-child> oh huh
<moon-child> I guess that's because for fusion it wants to use the rip of the branching instruction
<heat> O0 was actually more correct than O2
<mrvn> is that fusion a new thing?
<heat> clang played itself
<geist> that implies to me maybe it's using the ALU to compute the address maybe?
<geist> and thus steps on its own toes to get the flag results
<geist> moon-child: oh yeah thats true too!
<geist> actually that's probably it, the notion of what the RIP is is a bit more funky in a fused instruction sequence
<mrvn> geist: you don't think it has dedicated adders for address computations?
<geist> the uop cache probably stores a fused instruction at the start of the first of them
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<moon-child> I guess there's some subtlety because if the memory access faults you do have to point at the comparison op
<geist> and thus can't easily reconstruct the RIP on subsequent runs
<moon-child> even when not rip-relative
<moon-child> but that's off the fast path, so presumably easier to handle
<gog> hi
<geist> well, he compariso op wouild still be the base of the fusion
<geist> so no info loss there
<geist> it'd be if it needed to fault at the base of the branch, which it shouldn't be able to for normal instructoin reasons
<geist> so my guess is as it's running uops the RIP of thenext instruction is basically 'free' because it's part of the instruction dispatch mechanism
<geist> but it only makes sense if it's at the boundary of the original instruction
<geist> mrvn: re instruction fusion, that goes way back, though i dont remember precisely when it started showing up on x86 hardware. maybe late p4 era? core 2?
<geist> and dunno when amd got it
<geist> moon-child: it does beg the question what happens if an irq fires in the middle of a fused instruction, or if you have a single step debug going on, or even an instruction-address-match in the debug hardware
<geist> that has to throw a huge wrench in it
<mrvn> what actually gets fused? The cmp and branch?
<geist> yah
<geist> even on modern ARM hardware the optimization guides tell you what compare and branch instructions are fused
<mrvn> my guess would be that those turn of fusing
<moon-child> irq I would guess you just finish the fused op first
<geist> and also in ARM64 a sequence of address synthesis instructions can be fused to a single cycle
<moon-child> single step debug is more interesting though. I wonder how that's implemented
<heat> if (single-step) dont_fuse()
<geist> ie, `adrp + add` to synthesize a 64bit address gets fused into a single 64bit immediate load in arm64
<moon-child> maybe it rigs the decoder to inject an interrupt instruction after the next instruction or something?
<mrvn> moon-child: in the olden days the debugger would replace the next opcode with a BRK opcode.
<moon-child> what if it's a branch?
<mrvn> moon-child: the destination of the branch in that case. for conditional both targets
<geist> but this knowledge of what gets fused does matter of course, because you want to avoid breaking up the sequence, even if it would othrwise be a good idea (ie, adding space between two instructions that depend on each other0
<mrvn> that's quite ugly when it changes.
<moon-child> performance ain't portable
<heat> and you want to encourage these sequences too
<heat> cough cough clang
<geist> it'll be interesting to see what happens when folks start to build really high end riscv implementations and if fusion there will become register specific
<heat> why register?
<geist> ie, are you supposed to use t0 when synthesizing an address, and only if you use that register can it fuse it, etc
<mrvn> with t0 being the temp register?
<geist> in the case of conditional stuff the condition bits are written back to a GP register, so if you dont want the sequence to have any side effects you need to arrange for it to be overwritten
<geist> so i've seen for example the standard sequence of using ra instruction to compute the address of something you're about to branch to
<moon-child> I swear, riscv is going to implement uarchitectural flag renaming :^)
<clever> if a spec lacks instruction timing (not an mcu), then i can see how risc-v can have vastly different performance ratings, a naive implementation would just be 1 clock per opcode flat
<geist> which then has the effect of overwriting the result register
<clever> and more complex opcodes then impose a freq limit
<geist> but yeah in riscv a common pattern would be something like 'slt + beq'
<mrvn> Somehow I feel this fusing is cheating. For riscv why do risk when you want complex instructions (except encdoded as multiple risc opcodes)? On x86? It's CISC, why not have fused opcodes?
<geist> with a trashed register. you *could* for example do something cute like 'based on which t register you used, hint prefer taken or not'
<mrvn> I hate cpus that don't have general purpose registers. Even if it's only that some registers will be slower.
<geist> mrvn: well you'd ove riscv sicne it's the exact opposite of arm64 in that regard
<geist> only GP registers, nothing else
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<mrvn> not even stack?
<geist> not even stack
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<mrvn> I like that ARM doesn't have a hardware stack register, only a convention.
<geist> i forget the raw code sequence to get a copy of the current PC. but there's a pair of address calculation instructions, so probably something like 'adr x1, 0(pc)' or soemthing
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<mrvn> PC isn't a general purpose?
<geist> no
<geist> more importantly it's not even a register. it's simply PC
<mrvn> They tried that on ARM but there are a bunch of things you can't do with the PC. Architectually it's a bad idea to have the PC as general purpose register.
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<geist> yah they copied that from DEC systems, which tended to do that
<geist> ie, r7 on pdp-11 and r15 on vax
<mrvn> Seems so nice to just have "add pc, pc, #40" to jump somewhere. But building that into the gates gets more complex.
<mrvn> return from function? pop pc
<geist> ah 'auipc' instruction on riscv is how you can read the current PC if you wanted to
<mrvn> You should never need that. Except once at program start to relocate your code. :)
<clever> one trick ive seen somewhere (i think in arm), was to `bl foo:` and just `foo:` on the very next line
<clever> and now the addr of foo, is in `lr`
<geist> right, which on anything halfway modern is terrible
<geist> that's what you hd to do in i386
<mrvn> That's the x86 way
<clever> the branch prediction cant deal with that?
<geist> and it fouls up the call stack sinc eyou have an unbalanced call/ret
<geist> on i386 the solution is to call a little routine that reads the IP off the stack, then rets
<clever> but on arm, it doesnt touch the stack, so you can abuse it like that?
<mrvn> you can "bl get_pc" and make it a function with ret
<geist> no, the little optimizatoin in modern cpus that it uses to branch predict through the ret
<geist> so yeah it breaks the branch predictor
<mrvn> given the use case is to relocate your binary does that matter?
<geist> even riscv has a trick there, since ther'es no real ret instruction, just a `jal ra` but it says pretty specifically that if you indirect through 'ra' it should treat it like a function return
<geist> whereas if you use another register like t0 it should treat it as a regular indirect
<clever> the weirdest use of lr that ive seen is the centurion cpu6, where you basically have `ld r0, [lr++]`
<clever> and the ABI expects args to immediately follow the call/bl opcode
<geist> so they're leaving it such that the branch predictor can guess a bit based on the register you're using to what you intend to do
<geist> yah args after call are not that odd in older machines. bnchs was just saying they were working on a 68k machine that puts the args just after the trap instruction
<geist> probably a pretty similar sequence on 68k
<bnchs> yeah this is only for a specific OS for the 68k
<clever> and something i read about recently, that changes how i view 6502, is that the 0-page is treated like 256 bytes of registers
<mrvn> They stopped doing that when memory protection (MPU or MMU) was added.
<geist> an even older technique you see in machines where there was no hardware stack was to spill registers just before (or after) the call instruction
<mrvn> clever: the 0-page has extra, shorter, opcodes to access.
<clever> yeah
<geist> basically just dump spilled regs right there in the text seqment. doesn't let you recurse but at least gives you functions
<clever> previously, i hadnt thought about abusing 0-page like that
<mrvn> ouch.
<clever> i was thinking more in modern terms, where you overflow into the stack frame
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<mrvn> that is a major speed difference.
<clever> which is why i basically never did 6502 asm :P
<geist> yah 0 page it's quite frequent to set up a bunch of global arg registers there too for whatever binary you have.
<mrvn> Now what would be really nice is if you could set a base address for the 0-page.
<geist> ie, load the X Y of your drawing routines into some dedicated 0 page regs then jsr blit
<geist> mrvn: 6809 which is the successor to the 6800 that 6502 qwas kinda a fork of has exactly that
<zid> It's like a 256 element shadow stack calling convention :P
<clever> i recently went over the schematics for the vic20 and c64, and found drastic design differeneces
<geist> an 8 bit register that lets you set the 'direct page' which is what i think 6800 called it
<mrvn> kind of makes is random-access stack
<geist> actually now that i think about it 6800 may have had a relocatable direct page too
<clever> the vic20 does address decoding entirely with dumb logic gates, and a few 3bit -> 8pin decoders
<geist> but 6502 was intended to be super super simple
<zid> apollo AGC had a call and change memory bank instruction which is cool
<clever> while the c64 has bloody dram, and all address decoding in one magic black-box
<geist> fun thing that z80 does to assist with that: during dead cycles while the cpu is doing work it tosses out an incrementing address on the bus so the dram refresh logic ca use it
<geist> there's an internal counter in the cpu that's always running
<geist> actually i find it to make it kinda a nightmare to debug one with a logic analyzer since it's just continually throwing stuff on the bus
<clever> the PLA on the c64 seems to handle both dram refresh, and generating ras and cas cycles to the dram, when the addr targets ram
<clever> the other major difference i noticed, was just how the ram is handled
<mrvn> long live sram and vram.
<clever> vic20, just had a heap of 1024 x 4bit sram chips, and later models bodged some 2048x8bit chips in, with an OR gate to join bank/chip selects
<clever> but the c64, just has a pair of 64kb x 4bit drams, 8bit row, 8bit column, 4bit data
<geist> one of the countless 'build an 8 bit breadboard machine' folks on youtube is doing a very detailed z80 based machine and he refused to just use a gigantic modern SRAM and actually has a board set up for the dram logic in TTL
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<geist> kinda interesting
<geist> but he's almost way too detailed to be interesting
<geist> https://youtu.be/GMS8MQHRRyg a good sequence if yo have infinity time to watch it and want to listen to a droning british guy go on forever
<bslsk05> ​'Designing A Z80 Computer Part1' by Jerry Walker (00:45:08)
<geist> apologies if one of you is this guy
<geist> note the firt one is 45 minutes long
<geist> he's on part 23 now...
<clever> heh
<mrvn> geist: I'm more interested in building the cpu than the stuff around it.
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* geist nods
<geist> mrvn: you like amiga, this might be a fun read
<bslsk05> ​fabiensanglard.net: The polygons of Another World
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<mrvn> "With a rate of 4,000 bytes per milliseconds, blitting the BKGD buffer at the start of each new frame took "only" 8 ms." Copying memory has come a long way.
<mrvn> geist: I wrote a flight simulator for m68k with generated landscapes. flat shaded 3D scenes are fun with hardware.
<geist> yah a fairly beat up a500 just went up for sale locally that i'm resisting the urge to get
<geist> it being PAL helps a lot
<geist> a 1040st went up for sale last week that i resisted the urge
<geist> but it was also pretty pricey. i'd rather get an a500 or a1200
<mrvn> you can buy an A4000 board and chips.
<mrvn> I also love the hack to connect an RPi to the Amiga bus.
<clever> mrvn: the drivers in emu68 are an even bigger hack
<clever> the rpi mmio, is mapped into the guest addr space, and m68k asm pokes rpi registers!
<mrvn> I'm talking about the boards that connect the RPI GPIO pins to the amiga bus and makes the rpi the cpu card for the system.
<clever> yeah
<clever> emu68 uses that board as well
<mrvn> It's fun to see that modern CPUs can bit-bang the main systems bus with a bit of extra logic to get the timing exact.
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<clever> mrvn: the hardest part, is that the fpga doesnt really have enough cycles to over-sample the rpi bus, so it needs to be clocked by the rpi, and sample on the right edge of that clock
<clever> the whole thing is being pushed to the limit
<mrvn> you could always get a faster fpga
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<mrvn> I imagine an A4000 cpu card would need something better
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<Iris_Persephone> ok I am about to make a mistake
<Iris_Persephone> I'm actually considering using Rust
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<geist> well, i'd say it might make sense to be pretty proficient in rust already before trying to write an os in it
<geist> OTOH, yolo!
<Iris_Persephone> eh I'm about as proficient in Rust as I am in C :p
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<zid> ..could you write an OS in C? :P
<Iris_Persephone> not _yet_
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<geist> hey if you realize it's a challenge and are willing to take it on, SGTM
<Iris_Persephone> well yeah, obviously this is going to take years
<Iris_Persephone> but the journey of a thousand miles starts with a single step and all that
<kof123> i still feel spite is underrated
<Iris_Persephone> hmm?
<kazinsal> geist: hey, have you ever replaced any of the caps on your vax?
<zid> I'd just immediately start taking the steps, if it interests you
<kof123> i think k lange said once he was doing something out of pure spite lol
<kazinsal> I was fiddling around with some stuff on mine last night and then it shut off followed by the unmistakable smell of a capacitor giving up the ghost
<kof123> just tips from veterans lol
<zid> you won't know what the fuck you're doing until you fail to do it
<kazinsal> wondering if the power supplies on those things tend to go after thirty some odd years
<mjg> people claim failure is great because they fail!!
<mjg> true sigmas redefine goals to claim success
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<Iris_Persephone> programming out of spite is fun, I was so fed up with my MIPS courses that I reimplemented the whole thing in Python just to prove how east it is
<mjg> corp 101
<Iris_Persephone> s/east/easy
<mjg> thta's some 'nice guy' thing to do mate
<Iris_Persephone> MIPS is surprisingly fun as assembly goes actually
<Iris_Persephone> okay well not
<Iris_Persephone> like
<zid> because everybody loves delay slots
<zid> and load delay slots
<Iris_Persephone> all of MIPS in Python or whatever, just the program we were doing
<mjg> sparc moment!
<zid> cringe r.r. mips
<sham1> Ugh, Python is just the pits
<Iris_Persephone> hey I didn't choose it the uni did
<Iris_Persephone> and Python was the language I was most familiar with
<zid> yea everybody seems to use mips, that's what riscv was designed to do
<zid> replace mips in all those courses
<zid> then you wouldn't have issues trying to find vhdl or whatever
<zid> Like, I have a riscv logisim file, it's tiny and you could teach people with it
<Iris_Persephone> we're using MARS because this course is supposed to be "baby's first assembly code"
<zid> yea it's either MARS or SPIM
<zid> ##asm gets a lot of people asking HOW PRINT NUMBER?
<zid> because it has a print string swi
<zid> but they have no idea how to build a string, and how to implement sprintf %d
<zid> so I am at least vaguely familiar with them
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<Iris_Persephone> hold on isn't it just syscall with your number in $a0 and the code 1 in $v0
<zid> They have print string, they don't have 'print number' and don't realize it's possible to have a) non-mutable strings b) format numbers into strings
<zid> d) enough knowledge of mips to know division gives you the remainder, which you can use to implement it
<kof123> yeah it was tongue in cheek, "this sucks so bad i can do better" is a start of some things
<kof123> *but "..." is how some things start
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<zid> spim has print_int it seems at least, maybe it was MARS that didn't only
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<Iris_Persephone> what's the point of pseudoinstructions in a course that's designed to teach you how processors work on the low level
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<zid> The problem is how broad of a knowledge base you need to actually produce meaningful output
<zid> where you can actually do the assembly part
<zid> you ideally need to do away with assemblers, linkers, execution environments, mathematics, etc
<zid> I've seen a *lot* of people say "I am learning asm, how do x?"
<zid> and the next 8 hours are teaching them number theory and binutils instead
<Iris_Persephone> kof123: knowledge is knowing that what you're going to make is shit. wisdom is doing it anyway
<Iris_Persephone> oh god not binutils
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<sham1> At least number theory is useful
<zid> It's number theory they were already taught when they were 10 but just forgot, to be fair :P
<Iris_Persephone> what like
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<zid> place value
<Iris_Persephone> binary versus decimal representations?
<Iris_Persephone> oh god
<Iris_Persephone> that's even worse
<zid> 123 is one hundred, two tens, and three ones
<zid> once you internalize that, you can write sprintf %d
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<Iris_Persephone> is this in the concept of significant bits
<Iris_Persephone> s/concept/context
<sham1> Significant decimal digits
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<ilovethinking> is it a good idea to make my scancode array so that scancode_array[scancode] = character?
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<ilovethinking> so for example scancode_array[0x23] = 'H'
<moon-child> ilovethinking: input translation is a giant ball of beeswax if you want to do it right
<moon-child> I wouldn't worry about it too much
<ilovethinking> so i just shouldn't translate them for now?
<moon-child> no, you should translate. Just don't worry too much about how
<ilovethinking> so how shpuld i translate
<Mutabah> a set of scancode tables, like you described
<moon-child> what you proposed sounds fine. Though I would suggest handling shift ahead of time (so eg scancode_array[0x23][0] is 'h', [1] is 'H')
<moon-child> I'm just saying that this is not the big, fancy, proper solution; if that's what you want, you should plan to research more and add something fancier later; if, more likely, you don't care too much, then just be aware of that and act intentionally
<Mutabah> Lazy option is to have just two - one for no shift/caps, the other for shift/caps
<ilovethinking> but how do i actually implement it without wasting hours? cuz the scancode set is massive
<Mutabah> (More complex solutions would have lots of rules, with capslock only impacting letters - but shift impacting all keys)
<Mutabah> Grab someone else's?
<Mutabah> Although... there's only 101 keys on a standard US keyboard
<moon-child> yes, I was about to sa
<moon-child> y
<moon-child> just implement the normal ones
<zid> and you know, it's basically just hitting a-z a-Z 0-9 for 3/4 of it
<Mutabah> The scancodes are also ordered based on key position (on the original IBM keyboard afaik)
<ilovethinking> i won't implement released for now
<moon-child> isn't release just a bit in the scancode?
<moon-child> it is for ps/2, at least
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<Mutabah> Depends on the mode iirc
<Mutabah> it's either the high bit in the scancode, or it's a prefix byte
<kazinsal> it's high bit set on scancode set 1, 0xF0 prefix byte on set 2
* moon-child nods
<kazinsal> pretty sure it's the same 0xF0 prefix byte on set 3
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<moon-child> either way, not much effort. It's not like release x is a completely different code from press x
<ilovethinking> so i do this for every scancode?
<Mutabah> usually you define the entire array
<bslsk05> ​en.cppreference.com: Array initialization - cppreference.com
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<ilovethinking> but they aren't organized
<ilovethinking> OH WAIT THEY ARE
<ilovethinking> KEKW
<Mutabah> i.e. `KEYCODE array[256] = { [0x02] = '1', '2', '3', '4', ... }`
<Mutabah> They're organised based on the original IBM keyboard layout
<ilovethinking> [0x02] = '1', '2', '3', '4'
<ilovethinking> what
<Mutabah> Which very closely matches modern US
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<ilovethinking> i haven't used that syntax
<Mutabah> Iirc that's valid syntax - it starts at index 2 and works onwards, until another `[]` resets the offset
<ilovethinking> oh okay
<Mutabah> But you can just specify the zeroes manually
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<kazinsal> honestly the extended scancode sets are a good example of a fairly straightforward system to decode as a state machine
<kazinsal> good practice for later, much more complicated state machines
<mrvn> Also pick the keyboard mode with the simpler scancode array
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<ilovethinking> mvrn: the first onr
<ilovethinking> mvrn: the first one
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<ilovethinking> yay
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<zid> bleh I can't get vmware tools working
<gog> ilovethinking:
<gog> i got mine working too!
<Mutabah> ilovethinking: Always a nice feeling to get keyboard input working, even if it's a hack
<gog> i had a bug in my interrupt handling code
<Amorphia> gog: pog
<gog> my irq stub is made by a macro
<zid> ah I think I finally figured it out actually, gtkmm USE flag
<gog> and it had mov \irq, %dil
<gog> it was supposed to be mov $\irq
<gog> whoops
<zid> gog I need to make a proper virtual terminal so I can add mine
<zid> we need to port open-vm-tools, the vmware balloon driver, the vmware socket driver
<bslsk05> ​outerproduct.net: Why no one should use the AT&T syntax ever, for any reason, under any circumstances
<ilovethinking> gog: grats :)
<ilovethinking> Mutabah: yeah, i have no clue how i'mm planning to go about backspace/shift
* Mutabah is away (not here ...)
<mrvn> zid: are you actually using that over kvm?
<zid> moberg: I found out a really bonkers wtf in AT&T syntax (or maybe just gas, but that's basically the same thing) he doesn't mention
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<mrvn> ilovethinking: also consider ctrl, alt, super, hyper
<mrvn> (windows, menu)
<zid> it seems to have equs for DWORD WORD etc to 2, 1, etc
<zid> so me and someone spent like 2 hours tracking down a bug in some code that did mov dword [eax], 12
<zid> s/moberg/moon-child
<zid> which it saw as... eax with a displacement of 2
<ilovethinking> mrvn: how should i go about uppercase letters
<ilovethinking> ?
<zid> because of 'ptr' missing
<mrvn> ilovethinking: usualy each entry in the scancode table is an array using all the modifiers as index.
* gog points
<mrvn> zid: and that is why I like "move.w" on m68k
<ilovethinking> mmm
<ilovethinking> ill figure it out later
<ilovethinking> what should i work on next
<mrvn> ilovethinking: yeah, start with just two entries for no-shift and shift and think about it later.
<mrvn> ilovethinking: the timer IRQ and then multitasking
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<ilovethinking> timer irq? what;s that for
<ilovethinking> i mean what will i need it for]
<moon-child> some userspace application wants to eat your entire cpu and never give it up
<moon-child> but you want to be able to schedule it out and let something else run
<moon-child> timer interrupt lets you do that
<mrvn> or for sleep(5);
<mrvn> I would have done timer before keyboard because it's simpler to working than PS/2.
<ilovethinking> i have done too much already anyways, ps/2 keyboard hsouldve been the first thing but i have physical and virtual memory already
<mrvn> virtual memory is always the first because otherwise you have to rewrite everything else when you switch to virtual.
<mrvn> Plus on x86_64 you simply can't do without.
<ilovethinking> the timer sounds so complciated for now
<mrvn> the PIT is trivial to setup
<moon-child> it is trivial. But you can also get by just fine without, for the most part. Most applications are well behaved
<mrvn> you want to do cooperative multitasking? *shiver*
<moon-child> obviously a bad idea for a real production thing
<moon-child> but again, it more or less actually works in practice
<mrvn> On the other hand you9 have keyboard interupts. So you would preempt on key presses.
<moon-child> and deemphasising it helps avoid the notion that timers are related to scheduling. Which is important imo
<mrvn> true
<mctpyt_> hello! nice to find such an active channel about osdev
<ilovethinking> hi
<moon-child> (also avoids using timer instead of tsc for querying time, which is also to the good)
<ilovethinking> mrvn: trivial means not important?
<klange> 'trivial' in this context means 'easy' or 'not complicated'.
<sham1> "trivial". Left as an exercise to the reader
<SerHack> Hey, I was wondering if I can get any help. I'm getting a triple fault on loading a GDT table, which register should I check for Selector Error Code?
<gog> it'll be on the stack
<zid> also, just use qemu and tell it to log interrupts
<zid> it's easier
<gog> also that
<SerHack> I'm logging interrupts for that reason
<zid> -d int -no-reboot
<zid> and just looke at the v=00 e=00 stuff
<zid> you want the first non-smm interrupt, it'll say old = 0xfffffff, new = 0xe
<zid> or somethin
<zid> is it a 32bit or 64bit gdt?
<SerHack> yeah, I understood the old and new but I was getting out of mind where I could find that selector error code..
<SerHack> It's a 16bit one
<zid> a *what*
<zid> is that.. allowed?
<zid> gog: You're the GDT police, is that allowed?
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<gog> it's allowed but why you're trying to use 286-style protected mode is beyond me
<gog> dos virtual machine?
<gog> or just a thing you're doing?
<SerHack> Sorry, I do meant it's a 32bit-based GDT for switching to virtual protected mode 16bit
<gog> ok
<zid> All I can say to that is "glhf" because I have no idea how it works and what it's for
<gog> and you're not trying to use long mode?
<gog> because that's absolutely not going to work
<SerHack> gog: no, I'm not trying
<gog> ok good
<SerHack> :D
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<SerHack> I looked for the first non smm-interrupt but I did not know where to look for the SEC
<zid> SEC?
<SerHack> Selector Error Code
<zid> e
<zid> if it's a gpf
* FireFly . o O ( normally the SEC looks for you, )
<zid> what exception do you get?
<zid> on what instruction?
<SerHack> I get gpf
<zid> The processor pushes an error code onto the exception handler's stack. If the fault condition was detected while
<zid> loading a segment descriptor, the error code contains a segment selector to or IDT vector number for the
<zid> descriptor; otherwise, the error code is 0.
<gog> right but what are you doing when it the thing does
<SerHack> Specifically I get gpf on the instruction that modifies ds register, so I'm currently looking at gdt that might be wrong
<zid> then v is the selector number you tried to load
<zid> e*
<gog> i don't want to be gdt police
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<SerHack> okay, thanks for helping. I'm feeling like a noob but I guess it's worth the trial and error approach :D
<klange> gog: what if we let you drive around in a cute little Honda Today GDT police car like in "You're Under Arrest"?
<gog> ew no
<zid> I'll do it if I get to have an itasha to do it in
<klange> zid: Best I can offer is to throw you in the back of my Civic.
<zid> she gets a honda but I can't even get a skyline with a nakiri ayame wrap, smh
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<sham1> Wait, we have a GDT police?
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<zid> as soon as klange funds us
<GeDaMo> Did somebody mention funding? :P
<klange> The last thing I'm funding is a police force.
<SerHack> But it's GDT police
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<SerHack> zid: okay, I get e=0038, so it's a problem from idt, and not gdt.. ahhh
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* gog think
<gog> changing my build order breaks the build
<gog> curious
<Amorphia> gog: everything is interconnected, no entity stands alone >:o
<gog> my relocs changed :o
<gog> wtf is that
<gog> i think it's because -mcmodel=small applies to all TUs now
<gog> and the way i pass that object around might need to change
<gog> OR i can figure out how to apply a reloc like that
<gog> i didn't even realize that -mcmodel=small didn't apply to all my TUs
<gog> i gotta go back to work tho lol
<gog> oh
<gog> GLOB_DAT
<gog> soulja boy GLOB_DAT
<gog> lmao it was dumber than that, i was missing the object from the link command whoops
<gog> ok now back to work for real
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<heat> gog, hello goggy
<heat> GOTPCRELX is a GOT access that can be relaxed to a PC-relative one
<heat> to the direct symbol
<heat> see the ABI doc, they document it all
<heat> gog, it's B.2 of the latest x86_64 SYSV abi btw
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<gog> heat: i figured it out it wasn't that
<gog> i was very dumb
<gog> because of the.. unique nature of my build if it's missing symbols it won't complain all that much
<gog> and this is due to $(future reason)
<gog> now i'm working on a new problem
<ilovethinking> what's the pit timer interrupt number
<ilovethinking> 0x20?
<ilovethinking> because for some reason after unmasking it my pmm is sending it
<SerHack> ilovethinking: yes, it's 0x20
<ilovethinking> my pmm never fired anything and now after unmasking 0x20 it fires
<heat> why are you saying the pmm is firing an IRQ
<ilovethinking> llvm-addr2line -e kernel/kernel.elf ffffffff80000290
<mrvn> the pit fires a minimum of 18 times a second
<ilovethinking> "/Users/john/Desktop/Projects/cuteOS/kernel/memory/pmm.c:19"
<mrvn> no reason why it shouldn't fire inside the pmm unless you disable interrupts
<ilovethinking> oh okay
<ilovethinking> anyways
<heat> ok, so its firing on a random line
<ilovethinking> it pagefaults after
<heat> not a problem
<ilovethinking> firing 5 times
<heat> your interrupt handler is broken
<heat> probably corrupting state
<ilovethinking> what should my pit handler look like
<ilovethinking> cuz all it does rn is tick++ and eoi
<heat> you need to have a wrapper in assembly that saves and restores state
<heat> because that's just free state corruption
<mrvn> for now just increment a volatile (atomic for smp) variable and maybe display that in the corner of the vga display.
<ilovethinking> oh shit
<ilovethinking> heat: how does that work
<SerHack> By the way, I'm obtaining a gpf with e = 0030. I'm assuming it's caused by idt, correctly?
<mrvn> didn't you save registers for your keyboard interrupt?
<heat> imagine your pit_handler is something like: inc [tick]; mov eax, 0x20 outb blah, eax
<heat> the code that gets interrupted will get the eax corrupted
<ilovethinking> mrvn: i mean i save the refuster
<ilovethinking> registers
<ilovethinking> for every interrupt
<heat> ilovethinking, push everything, run handler, EOI, pop everything, iretd/q
<mrvn> so, problem solved
<ilovethinking> yes i ave tagt
<ilovethinking> am dumb
<ilovethinking> but why does it fucking pf
<heat> that's yours to find out then
<ilovethinking> hmm alright
<ilovethinking> because it seems like everything is alr
<heat> your kernel, your code
<heat> you could easily be misaligning something
<heat> or fuck up the push/pop order, or ...
<ilovethinking> no but i have my kbd/isrs set up already
<ilovethinking> so i think it should be ok
<SerHack> If I get an error number for the exception gpf that is 0030 (related to idt), how is that possible if I load a blank idt?
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<SerHack> 0030 is taken from e=... on qemu -d int
<gog> it means an interrupt is happening
<gog> and your idt is blank
<gog> when a gate descriptor is invalid it #gp
<gog> check if you're calling a soft interrupt or you have external interrupts unmasked
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<ilovethinking> SerHack: turn on qemu logging with -d int and then addr2line the pc
<SerHack> curious, I disabled all the interrupts via the instruction cli
<gog> ok
<ilovethinking> yeah so just turn on logging and see what interrupt is happening
<SerHack> I have already enabled logging, but what's that addr2line?
<SerHack> Oooh, IP --> code line
<ilovethinking> yes
<ilovethinking> very usefuk
<ilovethinking> useful
<ilovethinking> addr2line -e kernel.elf IP
<ilovethinking> replace IP with the ip
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<bnchs> hii
<SerHack> ??:0
<SerHack> mh, great
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<gog> IP is instruction poointer
<gog> pointer
<SerHack> yeah, the "??:0" is the output of addr2line 😂
<gog> then you're jumping somewhere off in the weeds
<gog> maybe due to stack corruption
<gog> stack misaligned, ret loads garbage ip
<SerHack> How could I check if my stack is corrupted?
<gog> are you using gdb with qemu?
<sham1> You could eyeball it with a debugger, yeah
<gog> you'll need to know where your stack is supposed to be
<gog> yes
<gog> or with qemu monitor if you can stop it in the right spot
<gog> but it's easy to make happen with gdb
<gog> or using the info from the debug output
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<SerHack> thanks for the suggestions
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<SerHack> okay, found the instruction that causes gpf
<ilovethinking> i'm literally looking at my code for 20 minutes straight and i can't see any retarded mistake wt
<SerHack> it's a jmp
<gog> a jmp
<ilovethinking> how do i cause a pf on purpose to test my idt
<gog> try to read or write any address
<gog> that isn't mapped already *
<gog> you will need paging enabled
<ilovethinking> wait to enable paging i should move pml4 to cr3 right
<gog> are you going to be in long mode?
<gog> are you already in long mode?
<gog> because if you are then paging is already enabled
<ilovethinking> oh ok
<gog> and you just need to find an invalid address to test
<ilovethinking> i just realized i never mov pml4 to cr3 after mapping my kernel
<SerHack> I was referring to my previous discourse, it's not an answer for you ilovethinking
<ilovethinking> i know
<ilovethinking> lol
<SerHack> oh lol
<SerHack> anyway a jump... maybe it's jumping to null?
<ilovethinking> why does it say symbol cr3 undefined
<ilovethinking> wtf
<mrvn> More likely it's jumping to the higher half address and there is nothing mapped there if you never map the kernel.
<mrvn> first time you don't have a RIP relative jump
<mrvn> still strange that you got this far at all
<SerHack> yeah, weird
<mrvn> ilovethinking: cr3 is no symbol
<ilovethinking> cr3 is a register
<ilovethinking> __asm__("mov cr3, %0" : : "r"(to_phys((uintptr_t) pml4)));
<ilovethinking> says cr3 is unfefined
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<mrvn> by the way: loading cr3 clobbers memory
* gog registers
* lav memories
* gog moves to lav
* mrvn throws a GP
* lav is overwritten with gay noises and triple faults
<gog> oops
<gog> oh ilovethinking is gone
<gog> i was gonna say idk if they're using intel syntax
<bslsk05> ​'Nathan Evans - Wellerman (Sea Shanty)' by NathanEvansVEVO (00:02:36)
* lav shants the shanty
<mrvn> reprogramming successfull
<mrvn> grrr argh
* gog drinks sugar and tea and rum
<mrvn> Note to self: When building space station with artifical gravity make it rotate to make it challenging.
<gog> are you playing ksp
<mrvn> watching Dark Matter
<gog> ohh
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<GeDaMo> Docking with a rotating space station is challenging in Elite :|
<mrvn> GeDaMo: at least there you do that along the axis and not from the side.
* sham1 threads shit up
<sham1> 50 minutes for a learning result? Yeah, how about no
<sham1> I hope that even with Python's gimped threads it'll become more manageable
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<heat> bah, llvm-objdump -d poorly formats riscv output so short opcodes get misaligned
<heat> annoying
<kof123> yeah but is it misaligned in color or not?
<heat> llvm-objdump does not have coloring, binutils objdump is the one who does
<heat> it's also much faster
<heat> binutils objdump miles clear
<gog> hi
<heat> hi
<lav> ih
<moon-child> hoi
<heat> hearts of iron to you too
<moon-child> am TEM
<moon-child> >_<
<gog> am CAT
<lav> meow
<gog> =^.^=
<gog> i'm rewriting code i don't need to rewrite i should stop
<heat> no
<gog> yes
<moon-child> definitely not
<gog> i deleted it
<moon-child> :\
<gog> stop the rewrite dead
<moon-child> anything which was not invented here is BAD
<moon-child> past gog? who knows wtf that bitch was thinking
<gog> i already invented it
<moon-child> probably trying to sabotage you
<heat> 100%
<gog> probably but she might have been trying to help me
<heat> past gog stupid, present gog modern brian kernighan
<gog> past gog: wise, considerate. present gog: clown, baby, fool
<heat> if time keeps flowing does that mean that present gog invariably becomes a stupid instantaneously? yes
<lav> present lav: silly little cat
* moon-child pets gog
* gog prrr
<GeDaMo> Remember that future gog knows where you live :|
<moon-child> oh shit
<moon-child> better move then
<gog> i'm not afraid of her
<gog> she's even more of a clown
<heat> 🤡
<zid> future me is an asshole so I do things to sabotage him
<mrvn> future gog is a you problem
<gog> nah
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<kof123> " not invented here is BAD" that's a good point, time seems left out of NIH (whether arguing in favor or against)
<gog> given infinite time i will invent everything
<zid> dirty bastard
* gog uninvents zid
<zid> I wondered who was spreading *that*, but knowing it was you makes sense I guess
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<mrvn> I only rewrite bad code not invented here. so everything. :)
<gog> :)
<mrvn> considering c strings bad makes it easy to judge NIH software
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<sham1> C strings bad makes it very easy to add one's own (better) string abstraction
<mrvn> malloc also returns zeroed out memory and zeroed memory must be valid nullptr.
<zid> 'better'
<zid> Yet in practice, you never see that
<mrvn> zid: std::string?
<\Test_User> why does any other string form need to be an abstraction
<\Test_User> ptr,len is a valid string with no abstractions needed
<mrvn> that's an abstraction
<sham1> ^
<mrvn> len, data is also a valid string
<zid> I don't bother with a real 'abstraction' because it's just too much work
<sham1> Not requiring O(n) to do length computation is already a huge win
<zid> to put a wrapper around everything that takes a struct string { int len; char *s }; everywhere you'd normally take a char *
<zid> sham1: 99% of the time, you don't need to do that, and .99% of the time you know the length anyway
<sham1> There's not much else in terms of abstracting you can do without automatic memory management. At least in a nice way
<\Test_User> you'd typically want to do that yes, but you don't need to struct {} it, leaving it as a non-abstraction
<zid> Yea that's what I said
<\Test_User> unless you also consider a buffer to be an abstraction
<mrvn> zid and 0.01% of the time somebody exploits it to steel your bank account info
<zid> I specifically don't bother creating an actual abstraction, I just deal with raw strings and side-channel the lengths around
<sham1> Well it is. It's a conceptual abstraction. There is no such a thing as a "buffer" in a computer
<zid> see: strncpy
<zid> strncpy doesn't take a pascal struct, it just takes a string + length
<mrvn> zid: that's about the worst function you could name: Warning: If there is no null byte among the first n bytes of src, the string placed in dest will not be null-terminated.
<sham1> It's trivial to write a pascal struct wrapper for strncpy
<zid> yes, yes it is
<zid> but it's still more work than not doing it
<zid> and if you have 1 wrapper you should really have every wrapper
<zid> so I just.. don't
<zid> because it's a huge waste of time
<sham1> I just let my tooling generate it from IDL
<sham1> :D
<mrvn> zid: it's easy to not have char* at all and only length prefixed buffers.
<zid> The only time I make a string abstraction is when I am writing very defensive code that *would* have to check the length of the string multiple times
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<zid> like if I am hanging strings off a datastructure then releasing it into the aether and the string comes back to me later in a different context and I can't side-channel the length in
<zid> I have to attach it to the string then and there
<mrvn> The problem with your approach is that one day you will forget.
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<zid> so to give a random example, I load a bunch of resource files and I load them all into a struct resource { struct level_data *d; char *filename; }; and then later I want to support dynamic reload of my assets by hitting f5
<zid> but they need to check for alternate forms like .png or .jpg
<zid> I *might* in that case, attach a length
<zid> but even then, unlikely
<zid> strings generally are loaded, manipulated and discarded in the same spot
<mrvn> for that it's good to have a { size_t size; size_t used; char data[]; }
<zid> so you can just have the length in an automatic variable
<zid> for the entire object lifetime of the string
<zid> less likely: The string's lifetime exceeds the life-time of the auto, double less likely: It exceeds it *and* I need to modify it from the end in future.
<mrvn> well, strings should be immutable.
<\Test_User> why, modifying in-place means you don't need to copy the whole thing (especially if it remains the same length)
<mrvn> \Test_User: why would you modify a string? use a buffer
<\Test_User> why have strings and not just buffers
<mrvn> because then you can use them as e.g. keys in hashtables without having to copy them all the time.
<mrvn> and place them in .rodata
<\Test_User> `const` buffers then
<mrvn> that's a possible alias for string
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<mrvn> variables should also be mutable, immutable or const.
<\Test_User> what's neither mutable nor immutable...
<mrvn> can be modified but by you
<\Test_User> ah
<mrvn> not by you I mean
<mrvn> immutable objects can be used as keys in maps or hashtables and such. Everything else you have to copy.
<mrvn> const is a contract by the function that the string won't be modified while immutable is a contract to the function that the string won't be modified later.
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<gorgonical> Woodworking in an apartment isn't easy, but sometimes it is fun and even worth doing. I built a desktop table for perching my keyboard/mouse on instead of random boxes and books
<gorgonical> The quest for ergonomics continues
<zid> osdevdev
<zid> where you develop furniture for doing osdev in
AmyMalik is now known as MelMalik
<mrvn> woodworking your keyboard is fun too
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<heat> good morning
<zid> heat thinks it's monday morning
<zid> he's very confused
<heat> i'm a bit slow
<Iris_Persephone> oh wow I totally forgot I left my client connected
<Iris_Persephone> heya guys
<mrvn> zid: how could a monday morning ever be good?
<zid> write yourself an os yet?
<zid> or me one?
<heat> we should all write an OS together
<heat> as a community
<heat> that will totally work, it's a new idea
<zid> Yea I can't see a flaw in that plan
<gog> ok so should my input come through a stream that's backed by a ring buffer
<gog> seems the most easiest way to implement that
<heat> gog
<heat> hi
<gog> hi heat
<heat> wanna come contribute to my operating system
<gog> as soon as i'm done with mine
<heat> i'll take whatever evil idea you're hatching up with the PLT
<zid> I'd go for a high water line, then panic() and delete the OS
<gog> you don't want it, madness lies this way
<heat> i think it's monday morning
<zid> Maybe I'll make a little text mode console thing
<heat> i am the way
<zid> my bochsvbe stuff just gets in the way
<heat> gog: if you were online on Discord I could send you great gifs
<gog> i am online
<gog> i am not online
<zid> you are not online
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<zid> glog should I quickly hack up a way to type
<gog> i'm going online
<gog> yes
<zid> not online
<gog> hack up anything
<zid> okay will you supervise
<zid> my eyes are bad, I don't have my adult supervision yet
<zid> okay you're sort of online now
<moon-child> WAITFREE
<heat> moon-child, u good?
<moon-child> heat: yes
<zid> how do git submodules work
<moon-child> fully automated luxury gay space waitfree concurrent ring buffers
<moon-child> zid: afaik, poorly
<zid> funny
<zid> how do I do it
<zid> I want my bootstrap repo as a base
<Iris_Persephone> it's not monday anywhere in the world right now heat
<zid> but not as a fork
<mrvn> heat: Lets call it communismos.
<heat> zid, git submodule add
<moon-child> git submodule add https://something something/
<moon-child> and then git submodule update --remote to update the pointer
<zid> okay done
<zid> cool
<heat> i usually just cd to the git submodule and git pull
<heat> then git add the results and commit
<zid> oh it made a dir called bootstrap that's not what I wanted..
<mrvn> gog: input is a device. Someone has to open it and read from it. Shouldn't you have a uring?
<gog> ¯\_(ツ)_/¯
<moon-child> uring? why u?
<moon-child> microkernel?
<Iris_Persephone> should probably get that checked by a doctor
<heat> zid, what do you want to do?
<mrvn> moon-child: Some user space program will open then device, like getty.
<moon-child> sure, but that's on a separate layer
<mrvn> moon-child: and for the in kernel layers you could just use the same ring structure
<mrvn> moon-child: do you create threads for device drivers?
<zid> heat: .
<gog> what's a device
<moon-child> mrvn: no
<moon-child> but my thingy is weird and not representative. And I abandoned it
<heat> zid, . what
<moon-child> .
<moon-child> that's it
<zid> that's literally it
<mrvn> gog: things that produces or consumes a stream and has maybe some other functions.
<heat> zombo dot
<moon-child> WELCOME
<gog> what if it produces and consumes blocks
<heat> welcome to dot
<moon-child> you can do .
<mrvn> gog: then it's a block device, slightly different functionality as that generally can seek
<zid> You can't have a submodule at the root of your repository because both .git folder would conflicts.
<zid> You must create your submodule in a subfolder.
<zid> okay so fuck submodules
<zid> we're forking
<gog> ah ok you can seek a block
<heat> yes zid, that's not how submodules work
<heat> if you're basing your work out of the "submodule", it's a fork
<zid> yes
<zid> I literally just checked the documentation because you didn't know
<moon-child> gog: ok so basically
<zid> stop trying to teach me things I already learned ahead of you
<heat> you didn't ask
<heat> you just said .
<moon-child> you have a write high watermark, and a write head, and a read high watermark and a read head
<mrvn> gog: for a char device I would pass the data in the ring and for block devices pass descriptors.
<mrvn> (pointers to buffers=
<moon-child> to write, you bump the watermark, write your shit, and then bump the head
<moon-child> should be waitfree, works in interrupt handlers, or multicores, or whatever
<moon-child> magic
<mrvn> works with plain kernel, with threads for devices, processes in a mycrokernel, user space programms.
<mrvn> MAGIC
<zid> okay so let's set up some interrupts I guess
<moon-child> also read/write are monotonic so you don't need multiword atomics. Can just sample read head to find out if there's any space to write to; no aba or w/e
<zid> what IRQ was keyboard?
<heat> 1 right?
<gog> my crow kernel
<gog> :thinking:
<mrvn> gog: it's black
<heat> zid, yeh 1 is keyb, 12 is mouse
<moon-child> yeah I think 1
<mrvn> caaaw caaaw caaaw
<moon-child> pit is 0
<heat> pit is also 2
<heat> irq redirection baby!
<zid> pit is 2 yea
<zid> cus my irq mask is usually 3
<zid> for keyboard and pit
<moon-child> mmmm
<heat> that would make it 0
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<wikan> does anyone have any manual with intel opcodes?
<zid> what are manual ones? what are automatic ones too while we're at it
<wikan> like "mv reg reg" E4 {xx} {xx}
<bslsk05> ​'The Pointer Sisters - Automatic' by El Broko (00:06:10)
<gog> there's the automatic
<Iris_Persephone> automatic opcodes execute multiple commands per pull of the trigger
<Iris_Persephone> banned in California
<wikan> i have intel instruction set reference paper book and it is good. Can't find pdf. The same title has completely different book
<wikan> i am asking for something helpful for someone who write a compiler
<zid> mjg you awake?
<zid> ask this guy in polish the fuck he's talking about for us
<wikan> do you want me to explain zid?
<bslsk05> ​www.felixcloutier.com: x86 and amd64 instruction reference
<Iris_Persephone> wikan: you're sure you're looking at the same edition and everything right?
<klange> wikan: Volume 2 of the Intel SDM, or even just this Wikipedia page: https://en.wikipedia.org/wiki/X86_instruction_listings
<gog> undefined reference yay
<wikan> i think the new edition of this book is different
<bslsk05> ​www.intel.com: Intel® 64 and IA-32 Architectures Software Developer Manuals
<wikan> in my intel book I have very well explained how many bytes every opcode needs
<wikan> for example mov has several versions and every version was explained, like -> OPCODE {N bytes} {N bytes}
<wikan> and this is what i needin pdf or html ;)
<mrvn> wikan: aked and answered. move on
<zid> heat: What's the best way to get an unused label name in inline asm
<mrvn> zid: 1:
<zid> I know I can do 'jmp 1b' to reference it
<zid> but I forget how to declare the label
<Iris_Persephone> jesus look at that article
<zid> oh right just 1:
<Iris_Persephone> I hate CISC architectures
<zid> hmm I broke rodata somehow
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<zid> I fixed, needed mcmodel=kernel
<zid> not sure what it was trying to do without that that was making silly relocs, but hey
<mrvn> zid: small would assume 0-2G addresses and large would assume 64bit.
<mrvn> so anything in -2G to 0 would need relocs
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<kof123> https://www.zdnet.com/article/ballmer-i-may-have-called-linux-a-cancer-but-now-i-love-it/ since the lines are blurry, i propose a compromise that will stand the test of time, and was loved before and still loved by both "sides": DeveloperDeveloperDeveloperOS
<bslsk05> ​www.zdnet.com: Ballmer: I may have called Linux a cancer but now I love it | ZDNET
<zid> good news, it crashes somewhere, idk why
<zid> That'll do for 2023
<mrvn> time to write your crash handler
<mrvn> double fault handler if x86
<kof123> bringing neckbeards and suits together, its very agile-sounding
<kof123> (but not in actuality, this is the genius: developers remain full power)
<heat> zid, you can't use 1: in inline asm