<doug16k>
the risetime at 3200 is at least 1/(1600000000*3). 208 picoseconds. 1.5V right? 7.2GV/s risetime
<clever>
\Test_User: my bloody router has 8gig of ecc ram and a dual-socket cpu, lol
<doug16k>
how's that for dv/dt
<\Test_User>
lol 8 GB for a router? did they decide windows server is best for routing stuff now?
<zid>
turns out when you only have 10 electrons
<zid>
moving them around changes the voltage a lot
<doug16k>
er, slew rate I mean
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<clever>
\Test_User: i repurposed an old rack-mount machine as a router
<doug16k>
yeah, the gate it drives is nC
<\Test_User>
ahh
<\Test_User>
I thought you meant something actually made to be a router
<clever>
na, this was originally part of the processing core from an xray machine
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<zid>
I remember the cutdown wrt54gs being annoying because it was only 4MB instead of 8MB :P
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<geist>
oh side note: turns out the ryzen server is stable once i disable some of the C power state things
<geist>
apparently it's just well known that some of the ryzens are a bit unstable without it
<geist>
been running for like 15 days since i flipped the bit in the bios
<doug16k>
ya I have cstate off
<geist>
also explained why if i stressed it harder it failed less
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<geist>
seems to be an artifact of zen 2s only. i haven't seen it on a zen 1 or zen 3
<doug16k>
you get better `perf` data without cstate anyway. you get swamped with samples in the mwait or something
<doug16k>
you have it on idle=halt too right?
<ornxka>
wow, they havent fixed cstates on ryzen yet? ive had those off since 2017 lol
<doug16k>
it's the VRM
<doug16k>
you can "fix" it by turning up the VRM switching frequency
<doug16k>
increasing it by 50kHz will fix most ryzens that fail prime95
<geist>
well it is an older chip too that i was pressing into use as a server
<geist>
my zen 3 machine is totally rock solid
<gog>
mew
<ornxka>
ahh, yeah ive had the same ryzen 7 1800x since it came out
<geist>
previously the server chip probably never ran long enough in any one setting to actually hit a failure, since i'm fairly religuous about suspending my desktop and whatnot when not using it
<doug16k>
geist, is it before 2xxx gen? you have to disable uop cache in linux on 1xxx ryzens
<doug16k>
it hardly changes performance. it mostly saves a bit of power
<geist>
3xxx
<geist>
it's a 3950x
<doug16k>
the older one I mean
<geist>
that *is* the older one :)
<doug16k>
oh
<gog>
i have a 4660H :D
<gog>
have i mentioned i love my ryzen
* geist
sheepishly admits to having too much disposible income
<doug16k>
I couldn't buy 5950x, my 3950x is OP already
<geist>
i had replaced the 3950x with a 5950x (which is really not much of an upgrade) and then decided to replace the 2700x server with the 3950x chip and then all the stability hijinks ensued
<doug16k>
it would be unnecessary as hell
<heat>
buy Intel: my Intel TGL dell laptop throttled agressively to 400 MHz under any sort of load
<geist>
2700x is a zen+ and 5950x is a zen 3. so the 3950x zen 2 is the problem. and in retrospect it never was 100% stable, even in a desktop role
<heat>
if you always throttle under load, it's always stable
<geist>
whereas the 5950x is totally rock solid desktop wise
<heat>
dell is a galaxy brain OEM
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<doug16k>
heat, it's very hard to find something that isn't allcore 4.3
<gog>
i had reservatioons about buying a lenovo but i'm satisfied with this
<gog>
dell is like why'
<heat>
doug16k, hm?
<doug16k>
you can expect 3950x to run about 4.3GHz allcore
<heat>
oh right
<geist>
part of the justification for the 5950x (though it was weak) was i *wanted* the 3950x as a server, sine it's serving as a VM host and having all those threads is nice
* CompanionCube
rips geist's threads
<geist>
which it does nicely
<heat>
400Mhz allcore sounds way nicer doesn't it?
<doug16k>
heat, oh I thought you were saying zens throttle. nevermind me
* \Test_User
pulls out his integrated graphics running at 300MHz
<\Test_User>
not exactly a real gpu but whatever :P
<heat>
it gets fixed with the latest linux kernel + thermald, but the frequency is still crap
<gog>
:p
<heat>
it barely turbo boosts
<heat>
and the thermals... yeah, not exactly well designed
<heat>
with the price of this laptop, I could get a 5950x 32GB system
<doug16k>
400?! wow. the lowest I have seen haswell go is 800, at 100C
<heat>
but noooooooo
<heat>
yes, 400
<heat>
at 50C
<doug16k>
how is that possible? it's 28W
<doug16k>
12-28
<heat>
I don't know how they fucked up the firmware setup, but they did, and linux struggled hard with this specific laptop
<doug16k>
do I need to convert it from intel units, so 28W TDP means 96W electricity?
<heat>
dell latitude 7420
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<doug16k>
and the rest of the energy is transported to another dimension
<heat>
lol
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<clever>
mrvn: power company blinked again, lol
<heat>
ryzen 5950x in a laptop when?
<\Test_User>
when you make your desktop foldable and strap a battery to it
<heat>
I don't want an i9-12900k, but a 5950x sounds nice
<heat>
the i9 would be like intel mbp thermals all over again, but x2 worse
<heat>
before you say: "oh, but having a 5950x in a laptop is not feasible", you just have to believe
<doug16k>
of course it is, it's not high wattage
<doug16k>
mine hardly even gets over 110W
<doug16k>
in prime
<\Test_User>
my laptop runs into "intel said no overclocking your cpu" issues before it runs into thermal issues, but it's also a low power cpu and won't break even if I take out the fan :P
<doug16k>
if you turn off turbo, it's 16 core 65W
<doug16k>
3.5GHz
<doug16k>
turbo on is about 110W 4.3GHz
<doug16k>
they would let it get hotter than I have it set up for. I have mine set to throttle at 75. it never gets to 70
<doug16k>
hardly goes over 65
<doug16k>
you can just set the max temp in the bios and it will throttle to that
<doug16k>
it's kind of amazing how high it still goes if you put it so low it is silly, like 60
<doug16k>
turbostat will tell you power information on zen2
<doug16k>
reads the counters
<geist>
Yah. 5950x is solid
<geist>
As i expected the 5950x is not that much quicker than 3950x but it does have a good 15% or so single threaded performance
<geist>
So for some games it’s not terrible. But in general it’s not a worthy upgrade
<doug16k>
that extra load store pipe is incredible
<doug16k>
can pair pushes
<geist>
But yeah with all cores lit up it’s about the same as the 3950x. Memory bound
<doug16k>
nuts
<geist>
Stuff like large compiles are within a percent or two
<geist>
Am a bit disspoint that AMD looks like will get into the high wattage battle with intel with AM5, but that seems to be the primary thing it unlocks aside from DDR5
<geist>
But so it goes.
<geist>
In the grand scheme of things it’s all good: competition
<doug16k>
battle about the LGA physical stuff?
<doug16k>
or you mean competitive
<doug16k>
thought you meant legal battle for a sec
<doug16k>
how much will DDR5 cost I wonder
<doug16k>
once everyone wants to buy it at once
<doug16k>
do you think usb4 will really just plug and play eternal pcie enclosures?
<doug16k>
external*
<\Test_User>
usb will probably do anything except simplicity
<doug16k>
you just plug in the usb4 cable from the enclosure, and poof, you hot plugged all its pcie?
<CompanionCube>
at least usb connector superposition won't return
<doug16k>
what happens if I have a pcie enclosure with a usb4 card and I plug a pcie enclosure into the card then hook the first enclosure to pc?
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<doug16k>
route through all that?
<\Test_User>
5* complixity and insanity
<\Test_User>
with 5 just being a random number, likely in reality will be more
<doug16k>
now everyone has to make their driver so robust, they can rip out the card anytime and not crash the OS?
<\Test_User>
until you figure out a way to mount ram over usb and the kernel was mapped to that ram
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<geist>
5 is right out
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<doug16k>
what happens if you rip out cards without doing the hotswap procedure?
<doug16k>
nothing good, right?
<clever>
usually bad things
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<doug16k>
then what happens if you rip out thunderbolt transporting pcie?
<doug16k>
should be the same right?
<doug16k>
something tells me that external pcie enclosures are too good to be true
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<\Test_User>
pcie over usb sounds like insanity to me :P
<doug16k>
\Test_User, their physical layer are almost the same
<\Test_User>
physical sure, but when you want to deal with the software side insanity happens
<\Test_User>
at least, probably
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<doug16k>
pcie is just packets, no reason you can't transport packets through usb
<heat>
yo dawg
<heat>
heard you like packets
<heat>
so now your usb packets have packets
<doug16k>
^
<\Test_User>
maybe I'm thinking of smth odd
<\Test_User>
s/odd/else/
<doug16k>
usb4 just includes thunderbolt right?
<doug16k>
I don't know how completely or whatever though
<heat>
i think so
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<doug16k>
half expecting a forum post saying they get frame drops when their GPU is on a shelf at the other end of the room over usb4
<clever>
LTT has already done that, with fiber extenders
<clever>
and he mentioned the length limit, was based on the timing constaints, not the signal levels
<doug16k>
need a NIC with a MOSFET that puts a 250mA 600ps pulse in and out of the gate to turn it on and off and needs the whole card to be one big heatsink
<heat>
i know some of those words
<doug16k>
you have seen 2.5Gbps+ cards right? whole thing is heatsink, usually
<geist>
yah the few 10gbase-t cards i've seen have pretty sizable heat sinks
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<geist>
on the order of 10 or so watts for the transceiver. apparently it's a bit reason it's hard to make large 10gbase-t switches
<geist>
though SFP+ transceivers that do fiber use far less power
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<curi0>
are there any methods to read BAR size which don't involve having to disable memory decoding through PCI_COMMAND ?
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<geist>
i dont know what PCI_COMMAND is in this case
<geist>
the usual mechanism for reading the bar size is to write all 1s to it and see which ones are 0s
<geist>
but then for resizable bars i dont know how that works. presumably there's some mechanism by which the device changes its size and you have to re-read it?
<geist>
that you'll probably have to consult the PCI spec and/or know what the device in question does. it may be nonstandard
<geist>
since presumably it started off by publishing a smaller BAR size at boot, and then you're trying to map something larger
<geist>
without telling the device that it can use the larger size, it doesn't know you're giving it more space, even if you write a new address to it
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<curi0>
">the usual mechanism for reading the bar size is to write all 1s to it and see which ones are 0s" sure that linux does that ? https://elixir.free-electrons.com/linux/v5.19-rc4/source/drivers/pci/probe.c#L177. i've adapted this code to uefi and it works mostly ok without disabling memory decoding (some issues but might be my problem)
<curi0>
nvm it does seem like it requires memory decoding
<curi0>
*decoding off
<zid>
That's precisely what that code does though?
<zid>
it sets mask to all 1s
<zid>
writes it, then has a comment about if they're still all 1s, the device is foobar
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<jafarlihi>
Is there a way I can get the PID that a given physical or virtual address belongs to on Linux without walking the page table manually?
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<mrvn>
you would have to walk every page table to lookup a physical. There is some per-page struct in linux.
<mrvn>
And VM structs for virtual
<mrvn>
A virtual address always belongs to the running process or the kernel. On 64bit you can just check the sign. On 32bit, no idea.
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<jafarlihi>
mrvn: What do you mean by checking the sign?
<Mutabah>
The 64-bit address space is split in half (usually). Top half is for the kernel, bottom half for userland
<zid>
canonical addresses <3
<zid>
addressing, I should say
<gog>
jafarlihi: the sign bit will be set for virtual addresses in the kernel space
<gog>
the "sign" bit
<gog>
aka it'll be >= 0x8000000000000000
<gog>
well not equal to
<gog>
because those bits are not available currently
<gog>
read up on what a canonical address is in amd64
<zid>
Learning osdev one reverse engineering snippet at a time :P
<zid>
I feel like most of the rest of us are ground up
<gog>
we don't need no wheel
<gog>
we'll make our own rounded rolling device
<gog>
it's not a wheel
<gog>
patent pending
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<mrvn>
gog: we shape the road to fit the wheel
<mrvn>
And you have to rent differently shaped wheels at every toll booth or you won't have a smooth ride.
<gog>
yes
<gog>
sort of like how railroads int he US were in the 1850's
<gog>
gauge changes
<gog>
so you'd have to transload the cargo at certain cities
<Mutabah>
They still are all over the world
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<gog>
yes
<Mutabah>
Australia has multiple gauges
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<gog>
isn't that because a few major railroads are only for iron mines to go to port
<Mutabah>
Nah, just different standards. I know there's a gauge change between WA and the eastern states
<gog>
oof
<Mutabah>
And WA's passenger rail is a different gauge (I think) to the cross-country and freight lines
<gog>
well that's fine passenger trains and freight trains really shouldn't operate on the same tracks anyway
<Mutabah>
True.
<mrvn>
Mines often had smaller gauges because wide tunnels are expensive.
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<gog>
mrvn: the big one in aus i'm thinking of, BHP or smth, is a regular railroad just for transfer from the mine to port, not from subsurface
<gog>
also these are surface mines
<gog>
mostly
<gog>
and they only carry iron ore because there's so goddamn much of it
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<Mutabah>
Almost an entire line of Perth's commuter rail is dual-gauge to handle the cross-country standard gauge trains (the commuter lines are narrow)
<gog>
sort of like some subdivisions of norfolk southern and other short lines in the US only carry coal
<mrvn>
Mutabah: are they going to remove one gauge when they completed dual-gauging everything?
<Mutabah>
Nope
<Mutabah>
Commuter lines have to stay narrow, too much infrastructure
<Mutabah>
and the interstate line is already made - so stays standard
<Mutabah>
that line runs something like >2000km (only dual for 50km ish) until it hits the broad gauge network in the east
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<kingoffrance>
"Mines often had smaller gauges because wide tunnels are expensive" "ramps are expensive!" -- cave johnson
<mrvn>
kingoffrance: If you digging a tunnel it doesn't make much of a difference if it's level or a ramp.
<mrvn>
+are
<mrvn>
I love elevators for mine carts though.
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<mrvn>
wow, learned some new C++ today: struct A { int x; friend bool operator==(const A &lhs, const A &rhs) { return lhs.x == rhs.x; }}; Didn't know you could define friends in classes.
<gog>
friemd
<zid>
capybara?
<gog>
yes
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<zid>
gog: Your name is very hard to tab complete, when are you murdering the three other users matching go.*?
<zid>
It's like jet li's the one, if you defeat them in combat you gain their letters
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<\Test_User>
imagine trying to tab autocomplete a name with only 1 easy character left to type
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<zid>
I'm going left for shift for : afterwards, or tab is adding it, depending on client, so it still saves time
<FireFly>
tabcompletes easily enough with most-recently-used tabcompletion order
<zid>
yea if only half my clients had such an advanced feature :(
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<zid>
maybe I should look into hex editing the shit out of mirc
<Griwes>
mrvn: yeah, we call those hidden friends as they are only found via ADL, and only when they classes are in the argument list, and defining operators that way reduces the overload sets that compilers need to deal with
<\Test_User>
ah yeah right 1 character for the name but then 2 more for the ": "
<\Test_User>
fair enough
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<gog>
zid: your complaint has been noted
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<FireFly>
I used mIRC once upon a time... but that was in a different life
<FireFly>
effectively
<FireFly>
tbh, you could probably implement it in mIRC script and override the tab keybinding or something
<FireFly>
(it'd be horrible though)
<moon-child>
we have mirc to thank for colour codes
<moon-child>
int x = 0; //and I used them for this hack, which was rather cute
<moon-child>
oh huh I didn't set any colour for comments?
<gog>
i saw grey
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<moon-child>
oh so term colour settings then
* moon-child
bonks unix and sighs
* gog
pets moon-child
<Ermine>
gog: may I pet you?
<gog>
yes
* Ermine
pets gog
* gog
prrs
<Ermine>
Now we have a small chain of petting
* moon-child
pets Ermine
* Ermine
prrs
<gog>
now it's a circle
<gog>
or a triangle i guess
<gog>
shapes were never my strong suit
<mats1>
yes daddy
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<Ermine>
gog: at least they are homeomorphic
<gog>
yes
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<FireFly>
I've ended up in a circle of headpats at least once before, heh
<bslsk05>
futurama.fandom.com: Lrrr | Futurama Wiki | Fandom
<gog>
mrrrr is something else
* vdamewood
gives gog a fishy
* gog
eat fishy
<moon-child>
never been in a headpat circle, but I was in a massage circle once
<moon-child>
was nice
<moon-child>
albeit a bit annoying, to massage while being massaged
<moon-child>
I wonder now if it would have been better to switch off odd/even
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<vdamewood>
I can pat my own head.
<GeDaMo>
Can you pat your head and rub your belly at the same time? :P
<gog>
yes
<vdamewood>
The trick is patting gog's head and rubbing GeDaMo's belly at the same time.
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<mrvn>
Has anyone implemented a custom new or allocator or container constructor for arrays where each array element can be generated differently?
<dh`>
do you mean specifically in C++, or in general?
<dh`>
the ocaml stdlib has constructor widgets for most collection types that take a function to call to generate each element
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<dh`>
so e.g. Array.init has type int -> (int -> 't) -> 't Array (where 't is a type variable and type variable arguments come are written at the front because ocaml)
<dh`>
I guess in C++ that would be something like array::array(unsigned n, void (*init)(unsigned n, T &fill))
<dh`>
but of course everything related to function pointers is a horrorshow in C++
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<clever>
mrvn: data records in haskellcan optionally behave like a tagged union in c(++), but with more safety, where the language enforces that you only access the right part of the union
<clever>
and those can then be put into a list like any other type
<dh`>
in haskell can you have lists whose elements are typeclass members, or is that not allowed? I can't remember
<dh`>
(that is, Ord t => [t])
<clever>
dh`: i think it requires that every member be the same type, and that type has Ord
<clever>
but, it could be a sum type: data Foo = FooA Int | FooB Word64
<dh`>
garden-variety heterogeneous lists make your type system undecidable, but it's more delicate for typeclasses
<clever>
instance Ord Foo where...
<zid>
ALL BELONG TO ORD
<dh`>
oh right, the syntax Ord t => [t] obviously means one t, since it's implicitly "forall t. Ord t => [t]"
<dh`>
so there's only one t
<clever>
dh`: basically, at compile time, it needs to know what t is, and where to find the function that computes the order
<clever>
yeah
<dh`>
there's no implementation reason you couldn't have a list of Ords of different types, the question is whether it can be typechecked
<clever>
and there can only be one type t
<gog>
praise the ord
<dh`>
of course, Ord is a stupid example for this topic, should have used Show
<dh`>
since that's actually useful
<clever>
i think it would still have to be a sum type
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<clever>
or a tuple, one min, you reminded me of some fun code i recently found
<dh`>
after typeclass elaboration it would be a list of pairs of "value" and typeclass dictionary
<dh`>
which is fine from an implementation perspective
<clever>
dh`: my rough understanding, is that its a list of types, that have a parser attached, so you can parse a file into type A
<mrvn>
dh`: replace that with a std::function
<clever>
and the 2nd part of each list element, is a function from A -> B
<clever>
so the end result, is always of type B, no matter what the file on-disk was
<clever>
it will then try each parser, and call the right A->B, for whichever parser worked
<mrvn>
dh`: your prototype is UB before C++20 by the way
X-Scale` is now known as X-Scale
<dh`>
mrvn: naturally
<dh`>
C++ lets you express all kinds of things, but only about 10% of it actually works at any given time
<mrvn>
It's interesting to see that before c++20 `new` was UB.
<zid>
^
<dh`>
clever: there are considerably less opaque ways to do that
<clever>
dh`: yeah, it took me several days to untangle that, just to know how to parse one of those types on its own
<mrvn>
how do I get uninitialized memory in c++20? They remoed `get_temporary_buffer`
<zid>
Anyone got a decent reason why amd64 sysvabi uses regs for varargs?
<zid>
That just seems like it's way more complicated to me?
<mrvn>
zid: because of implicit prototypes
<mrvn>
zid: can't have different calling convention depending on what the function expects to get
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<dh`>
for example, if your parser functions have type text -> maybe a (each with some specific a) you can have a list of type text -> maybe b and initialize it with [ parser1 >>= \b -> conv1, parser2 >>= \b -> conv2, etc ]
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<dh`>
and then you can at least read what's happening without needing to crossreference a dozen custom type combinators
<mrvn>
dh`: that should have some look-ahead function that says which parser to use
<dh`>
it's haskell, it'll do that on its own
<dh`>
if you were doing this in a sane language you'd do the whole thing differently anyhow
<clever>
let me get the final code i wound up writing
<dh`>
one of the cultural problems with the haskell world is a tendency for people to seek out super-concise "elegant" solutions and value them over comprehensible ones
<clever>
that entire line, then returns either a parse error, or a key
<dh`>
kinda like perl one-liners really
<clever>
yeah
<mrvn>
dh`: if you don't the compiler probably takes 10h to compile your code
<heat>
that's kinda like p y t h o n i c solutions
<doug16k>
amd64 does deviate slightly from just being the usual register variables, it expects al to be 0 or 1 to flag whether it passes float args, but it would be harmless if it got a 1 accidentally
<dh`>
also the whole thing is foolish because outside of whatever bubble the haskell guy is living in, you don't want to just throw every parser you have at the file to see if one sticks
<mrvn>
dh`: for the array alloc+init would you have just one signature that always uses a `callback(std::size_t i, T &uninit_obj)` or provide different overloads for when you want an index, or copy from iterator or initializer list array?
<dh`>
mrvn: beats me, I swore off C++ at least 15 years ago
<mrvn>
dh`: that was a different c++ back then
<dh`>
it's not better now, just different
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<doug16k>
zid, I *think* if you had old-style implicit prototypes (prototypes say ()) and it passed float arg, and you were unlucky enough for al to be 0, and it took vararg float, it wouldn't work right
<dh`>
anyway, given that it's C++ and you probably can't shoehorn the iterator version into the index callback easily, yeah you probably want a separate iterator version
<mrvn>
doug16k: extracting a vararg of a type that wasn't passed is UB.