12:42 <dormito> Hmmm. So the NXP App notes locations for the CTI base doesn't seem to work. However by chance I found out that the address for the ls1088 DO seem to work (I started modifying an ls1088 cfg to make the ls2160). Not sure if it's a sane thing to do, but I modified the ls1088's cpu loop (a copy of it, and techincally from an include) to be more of a "cluster" loop, and create 2 cpus per cti (the

12:42 <dormito> AppNote suggested their was 2 cores per CTI/dbg interface)

13:26 <Haohmaru> dormito, are you saying their docs are have wrong info?

13:37 <dormito> Haohmaru: maybe. I will note that I found the AppNote with a search engine, their product page doesn't seem to link to that app note (and it has "preliminary" marked on it).

13:45 <Haohmaru> some of their documents are only available when you have an account

13:45 <Haohmaru> but if they have wrong info - you should inform them ;P~

13:46 <dormito> yeah, I have an account. So far I haven't been able to find any mention of where the CTI/DBG bases are in their Reference manual, or the docs linked from the product page.

13:47 <dormito> but, as PaulFertser just recently informed me what CTI stood for, it's very possible I am missing something

13:47 <Haohmaru> dafuq is CTI? ;P~

13:47 <Haohmaru> CoreSight Talk Interface?

13:48 <dormito> "Cross Trigger Interface"

13:56 <Haohmaru> <close_enough.jpg>

14:32 <bencoh> dormito: you can often get/guess the addresses from the ROM

14:33 <bencoh> (using dap info on one of the ap_num iirc)

17:20 <dormito> bencoh: yeah, "dap info 0" and "dap info 1" report no ROM tables (which seems kind of suspect to me, maybe I have something configured wrong... but it seems I can attach to the A72 cores and single step them).