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<
matsievskiysv >
Hello!
12:03
<
matsievskiysv >
I have a JEDEC compatible NOR flash connected to my chip
12:04
<
matsievskiysv >
I can access it using `mdw` commands in RO mode
12:05
<
matsievskiysv >
But in order to write commands to it, I have to use a flash controller register
12:05
<
matsievskiysv >
Can I use cfi flash driver for it or do I need to write my own driver?
12:06
<
PaulFertser >
matsievskiysv: cfi driver implements protocol for CFI parallel flash.
12:07
<
matsievskiysv >
ok, thanks!
12:08
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PaulFertser >
matsievskiysv: so if your NOR flash is parallel, it's likely supported.
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12:10
<
matsievskiysv >
no, it'
12:10
<
matsievskiysv >
no, it's spi
12:11
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PaulFertser >
matsievskiysv: in cases like that usually the easiest way is to upload some bootloader to RAM that has the flashing commands embedded.
12:11
<
matsievskiysv >
I just don't understand how chip is accessed in cfi driver
12:11
<
PaulFertser >
matsievskiysv: CFI driver assumes the chip is on the bus directly, so it's accessed by memory reads/writes.
12:12
<
PaulFertser >
matsievskiysv: what's your target CPU?
12:13
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matsievskiysv >
microchip jaguar2c
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PaulFertser >
matsievskiysv: the easiest would be to init SDRAM by mww/mwb commands, then upload u-boot there, then use u-boot to flash.
12:16
<
PaulFertser >
matsievskiysv: alternatively, you can use a soic clip and use flashrom to write directly to SPI flash while keeping the target SoC in reset by pulling SRST to GND.
12:17
<
matsievskiysv >
yes, I currently use flashrom for programming
12:17
<
matsievskiysv >
I was just investigating the possibilities of flashing via jtag
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<
PaulFertser >
Alternatively, you can write an OpenOCD flash driver for this target.
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<
matsievskiysv >
Yes, I've seen it. It's kind of useless, just adds cpu register names.
12:53
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matsievskiysv >
Btw, it might be a good idea to split cfi driver into protocol and implementation parts
12:53
<
matsievskiysv >
Like rawnand driver in uboot
12:54
<
PaulFertser >
Probably
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