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<pdgendt>
Hi again, if in a jtag daisy chain, I have 2 controllers each with a separate RESET pin, a have to use the TRST strategy, right?
<PaulFertser>
pdgendt: hi
<PaulFertser>
pdgendt: all trst pins should always be tied together if you want to use them at all, and that's unrelated to reset.
<PaulFertser>
pdgendt: TRST is only to reset the _jtag state machine_, it should do exactly the same as the corresponding TMS+TCK sequence to go to the reset FSM state.
<pdgendt>
ok, so if I don't specify SRST and TRST it should handle resets with TMS+TCK sequence
<pdgendt>
My actual issue is that I am unable to write/erase in a daisy chain, reading seems to work. The polling for erase/write complete mask never succeeds
<pdgendt>
It does work with the single controller setup
<PaulFertser>
pdgendt: it should handle state machine resets (unrelated to SoC resets) with that sequence, yes (TLR: Test Logic Reset)
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<pdgendt>
PaulFertser: I can confirm from the logs that the TAP reset is used, but I do have an infinite loop after trying to call "avrf mass_erase" logs pasted @ https://pastebin.com/zYpNSaer
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<pdgendt>
PaulFertser: sorry to bother you, but any ideas on how I can debug the chip erase polling issue never succeeding?
<PaulFertser>
pdgendt: tbh, no idea really. Have you tried to ignore polling failure and just continue?
<PaulFertser>
pdgendt: I'd also check what the atmega manual has to say about that specific value you get from polling.
<PaulFertser>
Probably the device is locked and requires some special chip erase.
<pdgendt>
PaulFertser: hmn, I'll try to dig deeper.. I've actually ported a bitbang jtag interface into barebox for the same device, which works without issues and I don't see any differences AFAIK.
<pdgendt>
I always start with a JTAG reset all states (pulse TMS high 5 times), but I assume openocd driver does the same before enabling programming mode
<PaulFertser>
pdgendt: yes, it should, and you can see TLR in the verbose log.
<PaulFertser>
pdgendt: "JTAG reset with TLR instead of TRST"
<PaulFertser>
"JTAG TLR RESET to RESET"
<pdgendt>
can I do a manual IDCODE instruction to verify both controllers, so that the other is in bypass?
<pdgendt>
how should the openocd target order be if my HW is: OPENOCD (TDO) -> (TDI) atmega1284p (TDO) -> (TDI) atmega128 (TDO) -> (TDI) OPENOCD
<PaulFertser>
pdgendt: you can do manual "irscan" and "drscan" commands from telnet, they always put the other device in bypass.
<PaulFertser>
Can't remember but the documentation has a note about chain order.
<pdgendt>
I can the FAQ for JTAG TAP Order is confusing imho :)
<pdgendt>
-I can
<PaulFertser>
:)
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<pdgendt>
PaulFertser: I've managed to perform a chip erase using irscan/drscan commands, to it might be a timing issue?
<pdgendt>
as I type slow compared to running code :)
<PaulFertser>
pdgendt: might be. The code in src/flash/nor/avrf.c is quite minimal, you should be able to instrument it and compare the results.
<PaulFertser>
Not many people were using openocd for avr and even fewer had several of them in a chain.
<karlp>
I'm really curious what the hardware is? if you can say?
<pdgendt>
nothing special, we have atmega128 and atmega1284p connected to omap4430, all pretty old socs, the atmegas are dedicated peripheral controllers
<bencoh>
(now I'm wondering why you have an omap4430 in that design)
<pdgendt>
again, old board, the omap is running linux (and openocd)
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<karlp>
still interesting design putting two _different_ avr's on jtag like that :)
<karlp>
1284 was pretty expensive too.
<Haohmaru>
it has "a lot" of RAM
<Haohmaru>
iirc 16K
<karlp>
I'm going out on a limb and assuming these handle different "domains" and someone connected them together by saying " give me a jtag connection, you can each have your own cpu for your firmware team"
<karlp>
mostly just "more IOs" wasn't it? you got like, _two_ hard uarts, instead of 1 and shit.
<Haohmaru>
isn't it just 40 pins?
<pdgendt>
the reason for the different controllers was mostly due to certification
<Haohmaru>
i have that atmega in my drum machine, DIP variant
<karlp>
pdgendt: heh, the more you answer the more I think I don't actually want to know :)
<Haohmaru>
aww
<pdgendt>
karlp: yeah, I tend to agree :) the upside, we're updating devices in the field to get rid of old code/stacks, that's why I want to get openocd to work :)
<Haohmaru>
is it like "if you don't blink your LED with an fpga, i don't wanna know"
<karlp>
does certifcation know you're reaching in and touching them all together? ;)
<pdgendt>
sure 8-)
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