14:41 <lsneff> whitequark: with the ligeia rewrite, I got 625 MB vcd to load in about 6.9 seconds. It's no exactly the same as gtkwave loading a vcd, because I'm planning on the views for individual signals getting loaded lazily, but loading a small number of signals won't take long.

14:42 <whitequark> really nice

14:42 <whitequark> got any UI yet?

14:43 <lsneff> not yet, but soon hopefully

14:44 <lsneff> The new datastructures I'm using should mean I don't need to do anything fancy on the gpu and can just draw shapes on a canvas

23:17 <alanvgreen> Can Memory() from https://github.com/nmigen/nmigen/blob/master/nmigen/hdl/mem.py be used to synthesize single port block RAM memories? Perhaps by setting read_port.en.eq(~write_port.en)?

23:25 <mwk> not with yosys as synthesizer (this is a general yosys limitation atm)

23:25 <mwk> working on it, though

23:36 <alanvgreen> mwk: thanks! I'll keep an eye on progress. In the meantime we can simulate with dual port memory or, when that isn't feasible, use primitives