whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
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<agg> is there any easy way to check for overflow with signed arithmetic? with unsigned i'd just make a one-wider signal and check the top bit but that seems trickier with signed
<agg> (I guess cast inputs to unsigned and then add is probably the way...)
<mwk> for signed C = A + B, overflow happened iff sign(A) == sign(B) && sign(A) != sign(C)
<agg> oh, so just a separate circuit on the side to make an overflow bit? that's nice, thanks
<mwk> and that's the usual formula used to implement sign flags in ALUs, etc
<_whitenotifier-a> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JleHg
<_whitenotifier-a> [YoWASP/nextpnr] whitequark fce7297 - Update dependencies.
<_whitenotifier-a> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Jleb8
<_whitenotifier-a> [YoWASP/yosys] whitequark a317ece - Update dependencies.
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<cr1901> agg: You may also find this table useful: https://gist.github.com/cr1901/7c5cc6739dee36b82f1183ed57748401
<cr1901> With the caveat that the "borrow" bit is set if a borrow did NOT occur (65xx logic)
<agg> thanks cr1901!
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<agg> whitequark: should yowasp-yosys export yowasp-yosys-config? it looks like the cxxrtl.h header is in yowasp-yosys but I can't figure out how to locate it
<whitequark> it should but currently doesn't
<whitequark> essentially, yosys-config needs to be rewritten for yowasp
<agg> ah, should have known it wouldn't be that simple
<agg> hehe, import yowasp_yosys; os.path.join(os.path.abspath(os.path.dirname(yowasp_yosys.__file__)), 'share', 'include')
<agg> that'l do for now
<whitequark> yes
<DX-MON> so.. I'm trying to do this but can't help but feel with the error it generates, that I'm doing something wrong or I've found an nMigen bug:
<agg> DX-MON: your pins has pin 6 appearing twice, is that deliberate?
<agg> "1 3 6 7 2 4 *6* 8"
<DX-MON> it is not.. thank you
<DX-MON> the first 6 should be a 5
<DX-MON> ohey, now it builds
<DX-MON> wrong word.. it synthesises except for a known set of driver conflicts that are currently deliberate but which when I do proper memory region decoding on the peripheral bus will get solved
<cr19011> "It it closer to working as intended than before"
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<DX-MON> yeah, p.much
<DX-MON> been working on formalising the SoC I built so I can more flexibly change it and write new periphals.. which means doing busses properly
<DX-MON> figured I'd write a GPIO peripheral which is why the whole poking connectors and PMODs happened
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<cr1901> Link is broken
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<DX-MON> oh, I need to make the repo public.. I'll fix that shortly
<DX-MON> it's about time I made it public
<cr1901> Ahhh, that would explain it :)
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<DX-MON> that should now be fixed
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