20:26 <kbeckmann> i'm looking for examples of testbenches that are testing pipelined processes in a nice way. ideally i would like to have two functions that yield the timestep on their own. one that shifts in e.g. 30 cycles worth of data, and another process that asserts the correct output but which is delayed with e.g. 15 cycles.

20:27 <kbeckmann> or is it as simple as that i can add multiple processes with sim.add_sync_process(process) ?

20:32 <kbeckmann> yes it was.. sorry for the noise :)

23:37 <mwbrown> Anyone know if there is a way to extract the state string during simulation while using `with m.FSM() as fsm:`? I tried doing something like self.state = fsm.state, and that lets me yield it during simulation, but it only gives me the state number

23:38 <mwbrown> And since the state number seems to depend on the order in which it's used in the elaborate function, that seems less than useful, unless there's some sort of implicit dictionary the FSM creates to map the states to the internal values

23:40 <anuejn> mwbrown: there is fsm.decoding which maps the numeric values to strings

23:41 <d1b2> <dub_dub_11> well it definitely gets sent to .vcd

23:43 <mwbrown> Let me try that... I know the string goes into the VCD but I'm hoping to do simulation time asserts to make sure it's in the right state at the right time (trying to implement a JTAG TAP)

23:43 <d1b2> <dub_dub_11> ahh

23:44 <d1b2> <dub_dub_11> I suppose you could look at how the write_vcd function accesses it?

23:45 <mwbrown> I think `fsm.decoding` will work. Looks like it's an OrderedDict and I can just expose both of those to my sim testbench

23:45 <mwbrown> so I yield from state and then look it up in the dictionary

23:45 <whitequark> `fsm.decoding` is the right approach

23:46 <mwbrown> It worked, thanks!