00:18 <_whitenotifier-a> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±2] https://git.io/JZuux

00:18 <_whitenotifier-a> [YoWASP/nextpnr] whitequark 63d8196 - Update dependencies.

00:44 <_whitenotifier-a> [nmigen] akukulanski commented on issue #594: Time-0 race condition for simulation - https://git.io/JZuXf

04:01 <tcal> Is it possible to rename the reset signal of the default clock domain 'sync' to "reset" (instead of "rst")? I've tried the obvious stuff like m.d.sync.rst.name = "reset", but it doesn't seem to work, or maybe I'm doing that at the wrong point.

08:45 <Guest48> hi, can somebody please quicky help here? I am looking for a verilog/SV code generator. I have checked out nmigen and it looks pretty cool except that the generated Verilog code has a lot of "noise" (debug comments, unfriendly chars). Any way to configure these out?

08:45 <whitequark[m]> generating Verilog similar to what a person would write is not the goal of nMigen

08:48 <Guest48> Hmmm ok, I see. I guess I got that idea when reading from previous migen version maybe? Also I guess on the docs this is not clear enough maybe? See: Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys, or converted to human-readable Verilog code for use with

08:48 <Guest48> industry-standard toolchains.

08:50 <Guest48> maybe some recommendation on what would be the HDL oriented towards a verilog code generator tool? There is so many out there: veriloggen, pymtl3 , etc

08:51 <Guest48> I tried veriloggen but it is still a bit "rough" as it lacks real use case usage and documentation

08:51 <whitequark[m]> "human-readable" (as in, human-debuggable) is different than "similar to what a human would write"

08:51 <Guest48> yep, that is true alright