12:10 <d1b2> <Kergadon> Is there a way to include verilog code into nmigen? It seemed like there should be a way to interface them since yosys handles both, but I couldn't find any info on how to do so after about 30 min of digging.

12:32 <vup> @Kergadon, you can use instantiate foreign modules using `Instance` and if you use the platform build system you can use `platform.add_file(name, content)` to add (for example verilog) files

12:35 <d1b2> <Kergadon> Thanks!

13:44 <d1b2> <mtk> in simulation, is there any way for Passive process to wait for clock edge?

13:56 <whitequark> use `platform.add_file(filename, content)` to include Verilog sources, and then use Verilog modules through `Instance`

18:58 <d1b2> <tnt> Speaking of which, I was kind of surprised when I got a "duplicate module xxx" when I happened to name m.submodules.xxx somewhere else in my design.

18:58 <d1b2> <tnt> (and xxx is part of included verilog sources)

21:29 <whitequark> that's hard to avoid