_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<pftbest> Hello. I'm trying to get liteeth running on my versal board. I started with liteeth/phy/usrgmii.py but it turns out versal doesn't have IDELAYE3, only IDELAYE5.
<pftbest> As I understand I will need to dynamically load the delay into i_CNTVALUEIN instead of specifying it as a constant, but also the delay itself probably needs to be calculated differently
<pftbest> Does anyone has experience with IDELAYE5?
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<pftbest> Ok, figured it out. Turns out a single instance of IDELAYE5 can only do 1.8ns of delay. So to get 2.0ns you need to cascade a pair of IDELAYE5 + ODELAYE5 to get up to 3.6ns
<pftbest> Also, you don't really need to do dynamic loading, it seems to work fine even if you tie off i_LOAD=1 and put your constant in i_CNTVALUEIN, not sure if it's ok to do this, but works for me
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