_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<grabhanem> I have a question regarding using the LiteDRAM core standalone - it seems like when the core is generated with the --sim option, the CSR registers are laid out differently. This seems counter to the purpose of a simulation mode, since I can't directly simulate my boot code without changing it. Is there a way to get it to stay consistent?
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