20:46 <nucleotide> Hey everyone! I’m trying to use the existing c5pciephy from LitePCIe with a Stratix V board (with modifications to the PCIe lane count) and I’m facing a weird issue. When accessing the BAR from a host PC, all reads from addresses 0x0, 0x8, ... time out and the root complex returns all 1s. However, addresses 0x4, 0xC, ... return the correct

20:46 <nucleotide> data. I used SignalTap to verify that the TLPs are correct and they seem fine to me (for example, a read from the scratch register at 0x4 returns the completion TLP 0x12345678_00002104_06000004_4A000001). What’s strange is that requests and completions to multiples of the 0x4 addresses are sent twice, just with a different tag. There is only one

20:46 <nucleotide> request for the 0x0, 0x08, … addresses and then a time-out. I tried experimenting with 64 and 32 bit BARs and various options in the Altera IP, but the behavior stayed the same. I also tried using a 64 bit Avalon Streaming interface, but that didn’t fix it. Did anyone encounter this type of issue before or have a pointer what to try next?

20:46 <nucleotide> Thanks!