_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<RedMercury> i have a design with crossover uart and running etherbone, but when i connect to the terminal over wishbone all i get is newline spew, any ideas on how to debug?
<RedMercury> interestingly if i add a uartbone as well as using etherbone and connect to it with wishbone-tool i get a working litex bios
<RedMercury> i ran a wireshark trace with the etherbone dissector, seems that the terminal is reading from a csr that doesn't exist in csr.csv o_O
<RedMercury> well, did a clean build, the invalid address went away but the crossover uart is constantly saying it has data yet the only read is 0xa