_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Guest91> I'm trying to simulate a medium-sized migen design, and it's pretty slow (~500 cycle/s)
<Guest91> will I get a major (>10X) speedup with verilator or some other approach?
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