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<
Guest78 >
Hello all, I am trying to use LiteX to build a SoC on a Fomu board (Lattice iCE40 UP5K), but I am getting an error when I set --cpu-type to None:
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Guest78 >
$ ./lattice_ice40up5k_evn.py --cpu-type None --build
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Guest78 >
ERROR:SoCBusHandler:Region overlap between sram and csr:
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Guest78 >
ERROR:SoCBusHandler:Origin: 0x00000000, Size: 0x00020000, Mode: RW, Cached: True, Linker: False
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<
Guest78 >
ERROR:SoCBusHandler:Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False, Linker: False
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<
Guest78 >
Has anybody seen this before?
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