<davidlt[m]>
If you follow various RISC-V RVI stuff you would notice that Ventana Micro Systems is contributing various server specific parts (incl. in RISC-V Platform specifications)
<djdelorie>
I'm not as involved as people think I should be :-P
<davidlt[m]>
Yeah, I stopped following everything.
<davidlt[m]>
That "everything" started growing too much.
<davidlt[m]>
There are some many things going in parallel that it's hard to track.
<davidlt[m]>
But a lot of those bits will be ratified sooner than later (months away). Already most of it reached public review stage.
<davidlt[m]>
This will be a huge RISC-V update, with H, with V and others finally arriving.
<davidlt[m]>
Hopefully Profiles and Platforms are locked too in 2022.
<davidlt[m]>
I wish we could settle on "Server Extension"
<djdelorie>
I know about the V extension progress because it affects glibc
<davidlt[m]>
That will require H, Zam (misaligned access), time CSR implemented in HW, etc.
<davidlt[m]>
djdelorie: hopefully it RVV 0.7.1 doesn't cause any issues.
<djdelorie>
anything that creates new registers causes glibc problems
<davidlt[m]>
RVI is sending those Allwinner D1 boards with RVV 0.7.1, thus basically not compatible thing.
<davidlt[m]>
I don't exactly know RVV 0.7.1 vs 1.0.0 diff, but registers are probably the same.
<rwmjones>
i noticed they were doing some talks at the risc-v summit in sf