ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<mriesch>
arnd: mmind00: FYI david applied the patch that relaxes the checks on graphs for dt overlays to dtc. thereby we should get rid of nasty warnings that e.g. appeared in the compilation of our display overlay.
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<geertu>
rfs613: KS3.0, Yellow CPU = Exception Before Bootstrap Code is Loaded
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<rfs613>
geertu: well best of luck ;-)
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<cambrian_invader>
does Linux make any attempt to balance IRQs between cores?
<cambrian_invader>
I haven't touched my smp_affinity, and all my IRQs are going to the same core
<Xogium>
cambrian_invader: I think it does, yes. But don't quote me on this
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<cambrian_invader>
does the interrupt controller need to support it?
<cambrian_invader>
maybe my GIC is too old or something
<cambrian_invader>
I am thinking of just installing irqbalance, but it seems very strange for default behavio
<Xogium>
on that, I have no idea
<maz>
The GIC driver makes a point in *not* balancing interrupts.
<maz>
that's irqbalance's job.
<cambrian_invader>
ok, good to know
<maz>
specially if you have GICvx with x<3, allowing the GIC to send interrupts to multiple CPUs is terrible.
<cambrian_invader>
strange that irqbalance isn't in any of the "default" yocto layers though
<maz>
in embedded systems, you usually want to *exactly* where your interrupts are delivered. not leave it to some random userspace decisions.
<cambrian_invader>
well, this is... semi embedded?
<cambrian_invader>
there are too many interrupts and the final application is unknown
<maz>
it's your choice. the distro doesn't make it for you!
<maz>
(and yes, I agree. too many interrupts)
<cambrian_invader>
so if I say "devices A B and C will use cpu 0 and E F and G will use cpu 1" and the application only uses devices A B and C in some configuration then I have a problem
<maz>
no, you have a job!
<cambrian_invader>
:P
<cambrian_invader>
"come to cambrian_invader's IRQ and flyweel balancing"
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<maz>
at the end of the day, it is a trade-off between the price of irq rebalancing (cache thrashing, variable latencies) and a system that *looks* more balanced.
<cambrian_invader>
well, it is seriously a problem in my case, since everything goes to one CPU and it becomes the bottleneck
<maz>
then maybe irqbalance is the solution for you. you'll have to try.
<maz>
hopefully all your interrupts are directly routed to the GIC, without a mux in between...
<cambrian_invader>
I think so?
<cambrian_invader>
what would the point of a mux even be?
<milkylainen>
I thought that the kernel did a static balance on boot and you mostly needed irqbalance and the daemon to re-balance things in runtime?
<maz>
only route one interrupt to the GIC, and put a few hundred behind the mux, for example.
<milkylainen>
I mean, the kernel is fully capable to distribute irqs among cpus without a userspace irqbalanced?
<maz>
milkylainen: the kernel does no such thing.
<milkylainen>
maz: regardless of arch or what do you mean?
<maz>
milkylainen: "I thought that the kernel did a static balance on boot" <-- no, it doesn't.
<maz>
the initial affinity is left to the irqchip driver, and that's about it.
<milkylainen>
In that case the mask must come from somewhere. I have no irqbalanced and I have my irqs spread on all cores.
<cambrian_invader>
everything goes to CPU 0 which has 100% softirq usage
<cambrian_invader>
mask is set to f, but apparently that means 1
<maz>
cambrian_invader: yeah, you probably need to affinity adjustment. whether you want that to be done manually or automagically is your own choice.
<milkylainen>
cambrian_invader: which mask? I have a default affinity of f on my quadcore. And I have irqs running to all cores.
<cambrian_invader>
smp_affinity
<maz>
it's a shame that your Ethernet devices don't seem to have per-CPU queues, each with its own interrupt. that's usually a lot more efficient than having a single IRQ per device and having to balance that.
<milkylainen>
cat /proc/interrupts
<cambrian_invader>
well, they only have 2 queues anyway
<milkylainen>
oh, sorry, you already did that.
<cambrian_invader>
and the packet classification is pretty anemic
<cambrian_invader>
but yeah I agree not the best NICs
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