ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<robmur01>
ukleinek: given that the binding is basically broken to begin with, FWIW I'd go with removing the .dtsi entries
<robmur01>
(essentially, yes, the hardware does have an interrupt, but the way the rest of the binding is defined for that compatible it would impossible for a consumer to actually use)
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<mmind00>
ukleinek: yep ... have to agree with robmur01
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<epilys>
Getting this warning on an ampere altra:
<epilys>
(XEN) d2v0: vGICR: SGI: unhandled word write 0x000000ffffffff to ICACTIVER0
<epilys>
Does this mean some software interrupts inside xen guests won't work?
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<maz>
epilys: looks like xen doesn't handle some of the GIC registers (clearing the active state)
<maz>
epilys: should be easy to fix, but also should have too much of an impact if the GIC emulation resets clean.
<maz>
should *not* have...
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<ajb-linaro>
epilys which GIC is enabled (Xen has two, one home grown and one is a port of the Linux vGIC code)
<epilys>
ajb-linaro: I will check when I reboot to Xen, I'm not sure which GIC it is
<epilys>
maz: on what side must it be fixed? kernel or xen?
<maz>
epilys: xen, obviously. GICR_ICACTIVER0 must be writeable, as per 12.11.3 in the spec.
<maz>
ajb-linaro: this is GICv3.
<epilys>
maz: thanks for the pointers.
<maz>
ajb-linaro: ah, you mean it has two vgic implementations?
<maz>
I thought they had fixed that since...
<maz>
oh well.
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<ajb-linaro>
maz we await the mythical GICv5 when all IRQs are efficient, hypervisor interfaces are simple and complexity is reduced ;-)
<maz>
ajb-linaro: see you in 5 years then! :D
* maz
goes back to debugging the original GICv4 support, which has subtly broken between 6.5 and 6.6...
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