ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<geertu>
Is Marvell CN10 ARCH_THUNDER2?
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<apritzel>
geertu: if CN10 refers to "Octeon 10", then it's not
<arnd>
geertu, apritzel: I think Marvell decided to group it with ARCH_THUNDER2 despite it being completely unrelated
<geertu>
arnd: Thx, so ARCH_THUNDER2 is the right dependency to get rid of the enabled-by-default CN10 HRNG
<Amit_T>
OcteonTx series may be
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<arnd>
Octeon 10 (CN10K) appears to be based on the Octeon TX2 (CN92xx/CN96xx/CN98xx) family, which in turn is based on Octeon TX (CN82xx/CN83xx) in the old MIPS Octeon lineage
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<Amit_T>
there are ARMv8 based OcteonTX out there, I guess.
<geertu>
arnd: yeah, it appeared to me that way as well
<arnd>
This is different from Octeon TX2 (CN91xx), which is based on Armada 7xxx/8xxx in the ARCH_MVEBU family and ThunderX2 (CN99xx) in the Broadcom Vulcan ARCH_THUNDER2 family
<geertu>
arnd: Euh, ARCH_THUNDER2 says it's for Cavium's ThunderX2 CN99XX
<arnd>
drivers/crypto/marvell/Kconfig lists CN92xx and CN10K as "depends on ARCH_THUNDER2"
<arnd>
we don't actually have SoC support for either of those, so you could pick any one you want
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<geertu>
arnd: I don
<geertu>
't see that dependency in my tree. Do you already have the patch I'm planning to write? ;-)
<arnd>
geertu: I see you added that dependency in 42e6f351dcb0 ("crypto: marvell - CRYPTO_DEV_OCTEONTX2_CPT should depend on ARCH_THUNDER2")
<geertu>
arnd: That's for the TX2
<arnd>
geertu: if it'
<geertu>
Oh, it's also CN10. Well hidden
<arnd>
if it's for the TX2 cn91xx, it should be ARCH_MVEBU though
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<arnd>
drivers/crypto/marvell/octeontx2/ and drivers/crypto/marvell/octeontx/ appear to be two revisions of the same driver for the Cavium-lineage crypto unit, they should not have been separate drivers at all, and they are definitely unrelated to the Vulcan CN99xx
<geertu>
arnd: And 4cd8c3152edeb0a5 ("crypto: octeontx2 - Add mailbox support for CN10K") added CN10K, so it should be depends on ARCH_THUNDER || ARCH_THUNDER2?
<arnd>
geertu: no, only ARCH_THUNDER
<geertu>
arnd: but CN10K is ARCH_THUNDER2?
<arnd>
geertu: I think your 42e6f351dcb0 patch was a mistake, that was the only one mixing up ARCH_THUNDER and ARCH_THUNDER2
<arnd>
geertu: I only said that CN10K was listed as THUNDER2 because of this Kconfig entry, and I now think it should be reverted
<arnd>
so CN10K is ARCH_THUNDER, like all the other Cavium parts
<arnd>
maybe we should try renaming that one to ARCH_OCTEON
<apritzel>
does ARCH_xxx refer to micro-archs, or more to SoC platforms?
<arnd>
apritzel: it's always SoC platforms
<arnd>
apritzel: we have a number of those that switch out CPU cores between MIPS and ARM, or between custom cores and licensed cores
<apritzel>
I see, but we also depend core errata on those symbols, don't we?
<arnd>
apritzel: in some cases, there is only one microarchitecture, e.g. THUNDER2 is always Vulcan
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<apritzel>
that's what I was thinking, but all later chips from Marvell are somewhat different from the TX2, both SoC and uarch-wise, right?
<apritzel>
so THUNDER2 should be exclusive to the TX2 (which I am typing this on)
<arnd>
apritzel: THUNDER2 is never TX2
<arnd>
ARCH_THUNDER2 refers only to Vulcan, which was marketed as CN99xx or ThunderX2, but not TX2
<apritzel>
well, TX2 is a common abbreviation used here to refer to "ThunderX2 99xx"
<apritzel>
and I thought this was originally also used by Cavium, officially?
<arnd>
apritzel: you should try to avoid using that abbreviation unless you want to make it even more complicated
<apritzel>
arnd: old habits ...
<arnd>
I can't find any reference of Cavium using the TX2 name to refer to ThunderX2
<geertu>
arnd: first Google hit for "octeontx2 cavium"?
<arnd>
they did use the "Octeon TX2" name for their networking SoCs (as Marvell still do), presumably because it reminds potential customers of ThunderX2, but it was based on OcteonTX instead, which itself is based on ThunderX
<apritzel>
arnd: yeah, me neither, I think it was just sloppy wording here, plus Marvell/Cavium going full marketing with their naming later
<arnd>
geertu: OcteonTX was clearly just a smaller version of ThunderX, intended to replace the MIPS based Octeon products in network infrastructure
<arnd>
Cavium was in the process of producing their own "ThunderX2" when they acquired Vulcan from Broadcom. They kept the ThunderX2 name but used it for the Vulcan chip instead, which was much better and already taped out
<arnd>
This is the part that is well documented. The part that is not public is what exactly OcteonTX2 is, but from the available sources on the Marvell website and the source code, I'm 95% sure that OcteonTX2 uses the custom CPU core that was meant to be in the cancelled original ThunderX2
<arnd>
along with updated SoC components from OcteonTX
<arnd>
And "Octeon 10" in turn is a newer version of that part, but replaces the Cavium designed CPU cores with standard Neoverse N2 cores
<arnd>
which is different from ThunderX/OcteonTX (ARMv8 plus bits of v8.1), Vulcan/ThunderX2 (ARMv8.1), and OcteonTX2/CN91xx (Cortex-A72)
<arnd>
Interestingly https://www.marvell.com/products/data-processing-units.html only lists two original Marvell designs: Armada 7040 and its OcteonTX2 CN91xx successor. Everything else is Cavium legacy, including the CNF7xxx MIPS designs
<arnd>
all the server parts (ThunderX, ThunderX2/Vulcan and ThunderX3) are completely gone, along with the higher-end Marvell parts that were competing against OcteonTX
<arnd>
I guess Prestera 98DX73xx is probably still in the same family as Armada and ThunderX2/CN91xx, but there is no kernel support and it's probably much lower spec
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<geertu>
arnd: Ah, so my last 3 patches adding ARCH_THUNDER dependencies should be updated...
<arnd>
we should probably add 'depends on ARCH_OCTEON || COMPILE_TEST' to the various OcteonTX specific drivers in the tree
<geertu>
arnd: Yep. If they compile. I didn't check, as some have COMPILE_TEST && 64BIT in their dependencies...
<arnd>
I hadn't seen your patches yet. Let's maybe used your CRYPTO_DEV_OCTEONTX2_CPT patch first, then my patch, and then updated versions of your other patches
<apritzel>
arnd: speaking of which: isn't this "depends on ARCH_xxx" mostly wrong (for drivers)? As there is no *real* build dependency on those symbols? It's just convenience/economy that drivers those lines?
<apritzel>
arnd: I had this issue the other day when (out of sheer curiosity!) I ran a 32-bit kernel on a Pine64, and needed to set COMPILE_TEST to get pinctrl and clock drivers
<arnd>
apritzel: there are different approaches to this: gregkh generally doesn't like those dependencies because of the argument you make, but a lot of other developers including me do like them, as long as you can compile-test all drivers
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<arnd>
apritzel: I don't think anyone did that combination before, feel free to send patches to allow building those on arm32
<arnd>
what is the symbol for the dependency that you were missing?
<arnd>
apritzel: I guess you goit stuck at "depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST", right?
<apritzel>
arnd: yes, exactly
<arnd>
in that case, the ARCH_SUNXI dependency is correct, but the ARM64 dependency could be removed
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<geertu>
arnd: Do we really want to support booting 32-bit kernels on 64-bit SoCs? The 32-bit-under-64-bit kvm use-case has been killed a while ago
<arnd>
apritzel: obviously we don't want anyone to actually run 32-bit kernels on those, but if it works, we shouldn't block anyone from trying it for fun
<apritzel>
I am not sure if it's really worth a patch: I needed to badly hack U-Boot for that to work, fixing one bug there, and saw lots of complaints in dmesg
<apritzel>
plus I don't want to endorse that ;-)
<arnd>
ok, fair enough
<arnd>
I'd love to print a boot-time warning about booting a 32-bit kernel on a CPU that has 64-bit support
<apritzel>
I might go over the bootlog and check if there were actual bugs revealed
<arnd>
the situation is a bit messed up at the moment: in principle it should just work, but there are obviously platform specific bugs everywhere since it's not well tested
<apritzel>
PSCI is architecturally busted in this case, and there is no good solution for this
<arnd>
specifically, the 32-bit kernel is missing all the errata workarounds for known CPU implementation bugs that we have in arch/arm64
<arnd>
apritzel: what is the issue with PSCI?
<apritzel>
TF-A runs in AArch64 EL3, and doesn't know that U-Boot dropped from AArch64-EL2 into AArch32-EL1
<apritzel>
so secondaries are started in AArch64 EL2
<apritzel>
and this is not a TF-A problem, it's in the spec
<broonie>
There's an argument that that's something EL2 and lower ought to sort out, but it's not clear how.
<arnd>
There is also a stupid mismatch with the instruction set emulation for opcodes that got removed in ARMv8: arch/arm/ emulates unaligned ldrd/strd/ldm/stm but not setend/swp/swpb or cp15 barriers, arch/arm64 has the reverse
<arnd>
(correction: arm32 does emulate swp/swpb but still lacks the other ones)
<apritzel>
I think one sane way would be to tell TF-A to already drop into AArch32 EL2, but this is less practical, as you would lose the ability to launch 64-bit kernels
<arnd>
apritzel: any idea what the machines do that support both 32-bit and 64-bit kernels?
<arnd>
e.g. bcm2837
<arnd>
nsaenz: ^
<arnd>
are there different boot loaders depending on the kernel that gets loaded, or does the psci implementation manage to do the right thing despite the spec?
<ardb>
the problem is that u-boot drops into AArch32 EL1 but does not marshall the PSCI calls
<arnd>
apritzel: maybe we can find a byte sequence that is interpreted as a nop on aarch32 and a branch on aarch64, or vice versa, to let the 32-bit start_secondary drop into 32-bit mode if called in 64-bit mode?
<apritzel>
arnd: there is, just a sec ...
<ardb>
but there is some setup to do at EL2 before you can drop to EL1
<ardb>
which depends on implemented CPU features as well
<ardb>
i don't think we should add that to the arm32 kernel
<apritzel>
but yes, we came to the conclusion that this is not architecturally sane, and we tell everyone to run an arm64 kernel and arm32 userland, if they really must
<arnd>
ardb: the question is whether adding it would make it more or less likely that vendors ship bootloaders that allow running 64-bit kernels
<ardb>
right
<ardb>
they really shouldn't be using the 32-bit kernel in the first place, though
<ardb>
but i suppose we agree on that
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<arnd>
ardb: these are the arguments I've seen people use to justify using 32-bit kernels
<arnd>
- memory consumption, 64-bit kernels waste around 20 to 30 MB in the some configuration, mostly for unavoidable overhead such as 'struct page' and thread stack
<arnd>
- fear of bugs in the compat handling (mostly unjustified, but does happen with custom drivers)
<arnd>
- avoiding the need for separate toolchains to build kernel vs user space (doesn't seem important to me)
<arnd>
- user space bugs with missing alignment trap handling in arm64 (debian has run into this a couple of times)
<arnd>
- on Android, google requires using GKI kernels for all 64-bit targets, but not for 32-bit kernels
<ardb>
yeah the latter seems legit, due to the dubious fixups for load-multiple instructions
<arnd>
my feeling is that we should make sure we do the same thing for alignment fixups on both 32-bit and 64-bit kernels
<ardb>
i agree but this is controversial
<arnd>
if we can't get the silly trap handling into arch/arm64, we could attempt to do the reverse and stop handling alignment traps in arch/arm when running on a v8 CPU ;-)
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<ardb>
arnd: the fixup code decodes the opcode, which is fundamentally racy
<ardb>
no way the arm64 maintainers are going to take that code
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<maz>
geertu: 32bit kernels under 64bit KVM is definitely still a thing!
<arnd>
ardb: what is the differnece to decoding the setend/swp/swpb/cp15 opcodes?
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<ardb>
arnd: interesting, i didn't realize we had that code in arm64 already
<ardb>
i'm not sure i understand how it is guaranteed that the user memory address still contains the opcode that caused the exception
<arnd>
ardb: the only difference I see is that the instructions that are emulated are officially architected behavior in earlier versions but dropped in v8, while the alignment traps are for instructions that never behaved like this in hardware but were interpreted that way by Linux kernels
<ardb>
true
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<arnd>
ardb: I don't think we care if the instruction gets modified or not, if you trap on self-modifying code you have other problems already. The decision is either crash the task or do what the program almost certainly wanted
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<ardb>
arnd: there could be reasons that the opcode is gone other than self-modifying code
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<arnd>
ardb: I still don't see the problem: call_undef_hook() reads the opcode exactly once, at a time after the previous instruction has completed and before we look at the following instruction. If the opcode is readable and has an emulation handler, we run it, otherwise SIGILL.
<ardb>
arnd: i agree the window is really small, but that get_user() essentially reloads the opcode via the D-side that faulted via the I-side
<ardb>
arnd: ok so at least the get_user() will page the page back in if it was evicted
<ardb>
so it seems that you will only get a mismatch if userspace is doing something really dodgy to begin with
<arnd>
right, and I think only in cases that were already allowed relying on undefined behavior
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<geertu>
arnd: make sure to keep config ARCH_THUNDER select ARCH_OCTEON for at least one cycle, so people's .configs get updated by make oldconfig (but you probably already planned that anyway)
<arnd>
geertu: I wasn't planning for it, but I can add that.
<arnd>
TBH I don't think there are a lot of users on mainline kernels anyway: the few remaining ThunderX users likely use distro kernels that work, and I don't think OcteonTX2 support in the kernel is even complete enough to be usable
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