10:12 <milkylainen> I wonder if ARM is going to follow suit on the "Intel Software Defined Silicon"? Extensions under subscription license?

10:13 <milkylainen> Sounds to me like a whole new world of pain with instructions suddenly disappearing? Time based rental?

10:13 <milkylainen> *shrugs*

10:14 <HdkR> I see that MPIDR_EL1 is sanitized through the cpuid interface. Any reason to not expose the affinity level to userspace? git log just shows it was that way from initial implementation

10:37 <HdkR> I guess just use getcpu and get over it.

12:46 <broonie> HdkR: there's been issues with implementors not exposing MPIDRs that accurately reflect the topology and needing fixups from the firmware description so we don't want people relying on it.

13:10 <HdkR> Ouch

16:46 <mraynal> geertu: IIRC the nand controller drive matches the rzn1-nand-c* compatible, which is the opposite of what you said yesterday (or maybe my understanding is wrong)

16:49 <mraynal> when I read your sentence I understand : rzn1 is describing a SoC model/integration, while I suppose something like r9a06g032 describes the SoC family?

16:50 <mraynal> if this is true, then the order in the nandc bindings should be inverted and we should match against the r9a06g032 version

16:52 <mraynal> geertu: rfs613: I am actually able to boot the custom board with just a DT inspired from the r9a06g032-db + a proper NAND controller description. While writing it, it made me realize that the APB clock is named 'apb_clk' in the bindings and is listed second (the former being the external bus clock, such as the baudrate clock for uarts)

16:54 <mraynal> So I believe I am going to update the current proposal for the nandc, in order to match clock-names = "nand_bus_clk", "apb_clk";

16:54 <mraynal> Do you agree?

16:59 <headless> mraynal: I suggest that you drop "_clk"

16:59 <headless> because it's clear they are clocks from DT

17:01 <mraynal> headless: my intention was to match the existing nodes, but I'm fine dropping the _clk suffix

17:03 <headless> ah, if they're alerady matched by clock name, then dropping "_clk" isn't a good idea :-)

17:07 <headless> *already

17:09 <mraynal> I'll let geertu advise what is the preferred way to name clocks :)

18:05 <rfs613> mraynal: i can only speak for my own preference - no idea what upsteam policy is - I prefer to use the same names as in the Renesas reference manual. In this case it is Appendix C of R01UH0750EJ document, and they call it "nand_hclk"

18:06 <rfs613> (well, actually they call it NAND_HCLK but we can lowercase it without too much confusion)

18:08 <rfs613> NAND_HCLK is the APB clock, while NAND_ECLK is the external clock (that controls SPI bus frequency)

18:21 <geertu> mraynal: The discussion about "renesas,r9a06g032" vs. "renesas,rzn1" was about the toplevel compatible, i.e. the one for the root node? At least that was what I meant.

18:21 <geertu> In response to having a check for the board and/or SoC compatible value somewhere in (out-of-tree) ASM code.

21:40 <ukleinek> mripard: rumors say you might look into rpi-cm4-io.dts to add support for the i2c bus with the on-board rtc. If you do, feel free to look at https://paste.debian.net/1222648/ as a starter.

21:42 <ukleinek> mripard: I don't have a setup to test that at the moment. So feel free to take (and maybe improve) this change.