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[yosys] whitequark closed issue #36: What would be required to add support for SystemVerilog through Surelog+UHDM in YoWASP? - https://github.com/YoWASP/yosys/issues/36
<Wanda[cis]>
(I wrote some, and then decided that writing documentation would be best done as part of the in-hardware verification pass, which requires having some basic bitstream generation infra in place, so... next round)
<mabl[m]>
Yeah, it seems super impressive and cryptic at the same time. I guess I rather wait for it to be more mature
<Wanda[cis]>
(because at this point I could at most document my expectations for what all the bits mean, but this is just speculation grade with some of the more sketchy areas (sigh Spartan 6 I hate you))
<Wanda[cis]>
some of the virtex 2 stuff is already documented if you want to see what I'm aiming for
<mabl[m]>
Ah yes, that's far more parse-able! I just don't use any Vertex 2 😄
<Wanda[cis]>
well it is kinda ancient
<Wanda[cis]>
it was the obvious first target though
<Wanda[cis]>
minimizes the complexity × insanity product
<mabl[m]>
Always a good metric to aim for. That's really nice work. I would probably give up once realizing how large the mountain is. Keep at it.
<Wanda[cis]>
now that's why I heavily invested in automation.
<mabl[m]>
Yeah I saw that. Seems like there is one remaining reason left to install ISE
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<zyp[m]>
<whitequark[cis]> "zyp: do you have time to..." <- not this week, might have next week, but I don't mind Wanda doing it if she gets to it before me
<whitequark[cis]>
thanks!
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