02:08 <sagepolyester[m]> I have a DSP pipeline that im trying to simulate right now that uses this basic test bench currently:... (full message at <https://catircservices.org/_irc/v1/media/download/AacGhMryg83RcHAgNwgc8BZmauAJDJSR4ncucDtH0VFZQu2KHyBrg75pvqV6W8JbZk2yVIlZ91ee72ADPVxFBSpCeS0RjyCAAGNhdGlyY3NlcnZpY2VzLm9yZy9wSHZPQ3JvZkVxVXd2T2tVY1dBTG5FUlc>)

02:26 <sagepolyester[m]> is it as simple as adding another non-critical test bench that just awaits the clock edge and grabs a sample when the stream is ready+valid?

02:30 <whitequark[cis]> sagepolyester[m]: yeah that should work just fine

02:35 <sagepolyester[m]> 🤩

08:03 <meinhard[m]> I found it quite convinced to inherit from DUT and add all simulation-only logic to the derived class.

08:03 <meinhard[m]> Is there any possibility to assert on the current state of a FSM (e.g. `assert ctx.get(dut.m.fsm.ongoing("state_a"))`). I figured out that the FSM is added to `self._generated` (`self._generated[name] = fsm = FSM(fsm_data)`), but can I access it from the testbench?

08:40 <meinhard[m]> s/convinced/convenient/

08:40 <meinhard[m]> * I found it quite convenient to inherit from DUT and add all simulation-only logic to the derived class.

08:40 <meinhard[m]> Is there any possibility to assert on the current state of a FSM (e.g. `assert ctx.get(dut.m.fsm.ongoing("state_a"))`). I figured out that the FSM is added to `self._generated` (`self._generated[name] = fsm = FSM(fsm_data)`), but can I access it from the testbench? edit: convenient

08:41 <meinhard[m]> s/convinced/convenient/

11:39 <_whitenotifier-4> [amaranth] rroohhh opened issue #1538: Document FIFO properties - https://github.com/amaranth-lang/amaranth/issues/1538

11:45 <vup> meinhard[m]: if you store the fsm object you can use the `fsm.ongoing` function somewhere else: https://paste.niemo.de/raw/emivequsaj.py

11:53 <meinhard[m]> fantastic, thanks.

12:58 <_whitenotifier-4> [amaranth] gatecat opened issue #1539: Iterating over `View`s of structures - https://github.com/amaranth-lang/amaranth/issues/1539

17:11 <jorolf[m]> Apparently you can't use AsyncFIFOs with falling edge clock domains? Are there any downsides to instead inverting the clock signal of my domain? Or is there a better way?

17:12 <jorolf[m]> * Apparently you can't use AsyncFIFOs with falling edge clock domains? Are there any downsides to inverting the clock signal of my domain instead? Or is there a better way?

17:20 <jorolf[m]> And also kind of related to that: The created FIFOs are all named U$XX. How can I avoid that? Is that happening because I'm creating the FIFOs inside of a list comprehension?

19:47 <whitequark[cis]> <jorolf[m]> "And also kind of related to that..." <- it's because you're using m.submodules +=

19:48 <whitequark[cis]> without providing an explicit name like m.submodule.x =, or m.submodule["x"] =