<Wanda[cis]>
there needs to be a follow-up PR that detects inout misuse btw; the current code only detects proper output-output conflicts
<Wanda[cis]>
actually I'm going to add an enum to this while I'm at it
<galibert[m]>
Catherine: there’s no cdc if two domains are built from the same clock but with different enables right? There could be tight timings, but there’s a low boundary
<Wanda[cis]>
alright, added an enum and also improved the auto-port feature for Component to force port direction
<whitequark[cis]>
galibert: yes but we don't have EnableSignal() yet
<whitequark[cis]>
i hate that i knew the number offhand lmfao
<Wanda[cis]>
... you know the situation is bad when you start remembering issue IDs
<Wanda[cis]>
relatedly, found another minor bug: AssignmentLegalizer doesn't preserve source locations, so the driver-driver conflict messages tend to involve _xfrm.py
<Wanda[cis]>
but then it's on the chopping block already anyway, so...
<Wanda[cis]>
also conflicting with a pin gives you a source location in the bowels of XilinxPlatform or whatever instantiating the io buffer
<Wanda[cis]>
I suppose that could be improved by taking the sourc location of the resource in platform definition file or something?
<Wanda[cis]>
oh right, we didn't even have Instance locations before NIR
<_whitenotifier-7>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 40d495f - Deploying to main from @ amaranth-lang/amaranth@b30c87fa3eeef0373a6abf68e456f5eef4154790 🚀
<_whitenotifier-7>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 05c82cc - Deploying to main from @ amaranth-lang/amaranth@24a392887af19a9d013252759ec209d5a91a378a 🚀