<whitequark[cis]>
not only it's platform-specific and therefore should be done during elaboration, but it also gives you new and exciting opportunities to completely break your design
<tpw_rules>
i see
<tpw_rules>
do you think there any generic enough ones to elevate beyond that?
<whitequark[cis]>
there are some that are interpreted by yosys itself (which we use for verilog emission), but these are also kind of the ones we should probably not allow to set
<tpw_rules>
has anyone put together a pipelining solution for amaranth? not automatic but enough so that i don't have to count out cycles
<tpw_rules>
i have a couple ideas i might fiddle with, but immediately i'm not sure how to avoid creating a mess for elaboration if i want to be able to use it during elaboration
<whitequark[cis]>
elaborate?
<tpw_rules>
i guess amaranth is not multi-threaded, if you instantiate an Elaboratable in an elaborate method, then that Elaboratable's elaborate method cannot start until the current elaborate method is finished
<tpw_rules>
i'm supposing i want to say like m.pipeline_helper = ph = PipelineHelper() then like ph.add_signal(whatever), then have PipelineHelper's elaborate method connect everything up
<tpw_rules>
but the amaranth elaboration order is not defined
<tpw_rules>
but like i said i think i can depend on the fact that PipelineHelper's won't be called until it's done being used in that scenario
<tpw_rules>
because otherwise there would be timetravel
<whitequark[cis]>
I have thought about doing eager elaboration (i.e. the moment you add a thing to m.submodules
<tpw_rules>
hrmph. well i can add a warning to not add it until you are done. i hope you are not thinking to make it so eager as to be done in the constructor
<whitequark[cis]>
in the constructor?
<tpw_rules>
so that somehow it happens when PipelineHelper() is constructed
<whitequark[cis]>
that was how migen worked
<whitequark[cis]>
and it was awful
<whitequark[cis]>
amaranth has two phases: construction and elaboration
<tpw_rules>
i think it's too late for me to be thinking as cogently as i want. ima try some stuff tomorrow and maybe invite comments in a future meeting
<tpw_rules>
thanks as always for listening and the info
<_whitenotifier-7>
[amaranth] whitequark closed issue #641: Attributes are not properly applied to IBUFDS (and possibly other primitives) in Xilinx platform - https://github.com/amaranth-lang/amaranth/issues/641
<_whitenotifier-5>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 1a06ea0 - Deploying to main from @ amaranth-lang/amaranth@10117607a3fb6a78ed1136f8b5c6e40741083c62 🚀
<_whitenotifier-7>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 1777516 - Deploying to main from @ amaranth-lang/amaranth@6f44438e585dd54a89c0112732710b389e25a71b 🚀
<Wanda[cis]>
oh lol, the hdl.xfrm commit message got outdated in the meantime
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<cr1901>
line 852 and 883 of _nir.py, respectively
<cr1901>
looks like it GH decides to hide it from default view b/c large diff
<whitequark[cis]>
cr1901: that is a typo
<whitequark[cis]>
cr1901: and this yeah
<cr1901>
I've been relearning ReST for Sentinel docs (and "borrowing" the parts from Amaranth's conf that work for me.) I thought maybe the underscore was meant to be a link or something (missing the `` for multi word links)
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<_whitenotifier-5>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 20ee436 - Deploying to main from @ amaranth-lang/amaranth@84709e2f00901d536ec99947efb2ad2f35ff8548 🚀
<_whitenotifier-5>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] f72f379 - Deploying to main from @ amaranth-lang/amaranth@18e5bcd6f72c0e95c9bc39ee04d25bdba2874532 🚀
<Degi>
In lsusb I have two devices showing up as "ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC", one an ECP5 EVN and one ECP5 Versa. In lsusb -vvvv one shows up as "iProduct 2 Lattice ECP5 Evaluation Board", another as "iProduct 2 Lattice ECP5_5G VERSA Board". Amaranth with FPGA1.ECP55GEVNPlatform().build(SERDESTestbench1(), do_program=True, nextpnr_opts="-r") says "Error: unable to
<Degi>
open ftdi device with vid 0403, pid 6010, description 'Lattice ECP5 Evaluation Board', serial '*' at bus location '*'"
josuah is now known as F4JNK
F4JNK is now known as josuah
<Degi>
nvm the issue is probably with a missing udev rule
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<Degi>
(yes, that was it, adding SUBSYSTEMS=="usb" ATTRS{idVendor}=="0403" ATTRS{idProduct}=="6010" MODE:="0666" fixed it)