<whitequark[cis]>
<galibert[m]> "Python side cond or netlist side..." <- what do you mean netlist side?
feldim2425 has quit [Ping timeout: 260 seconds]
polymerizedsage has joined #amaranth-lang
<polymerizedsage>
heya
<polymerizedsage>
im poking around trying to get amaranth to run a build inside a docker container
<whitequark[cis]>
hi!
<whitequark[cis]>
we have a function BuildPlan.execute_local_docker nowadays
<polymerizedsage>
yes!
<polymerizedsage>
i am trying to use it but getting stuck and im not sure if its because im missing some docker knowledge or because the command it executes should be changed
<polymerizedsage>
so execute_local_docker calls my build_top.sh by putting it in front of "sh"
<polymerizedsage>
and my build_top.sh then drops into bash
<polymerizedsage>
but when i call the docker run command it just drops into an sh prompt and then exits
<polymerizedsage>
Im more familiar with calling bash scripts in docker along the lines of sh -c some_script.sh
<whitequark[cis]>
that's interesting. which image and toolchain are you using?
<polymerizedsage>
its an ubuntu 20 image i have built myself to use the lattice radiant toolchain
<whitequark[cis]>
okay, i see
<whitequark[cis]>
can you share the image?
<polymerizedsage>
eeh im not sure how the radiant licensing works but im probably not supposed to send a image with the software in it, I can send the image without the tools as thats probably fine and should be enough to reproduce
<whitequark[cis]>
I already have a Radiant license
<whitequark[cis]>
(it came with one of my boards, I can send you a proof if you'd like)
<polymerizedsage>
ya I can probably send something then that you can add your own license to. Its quite hacked together currently let me see if I can put it into a state that would be straightforward to reproduce the issue
lf has quit [Ping timeout: 264 seconds]
lf has joined #amaranth-lang
<polymerizedsage>
It looks like its purely an issue with how im managing the entrypoint script to my container. Ill lyk if i run into further trouble but I dont think this is an issue with amaranth just with my docker
<_whitenotifier-c>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] b075c45 - Deploying to main from @ amaranth-lang/amaranth@572a60d8389e5aef72886ea4bc4d5b62d450cdff 🚀
polymerizedsage has quit [Ping timeout: 250 seconds]
<_whitenotifier-3>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 1e527a5 - Deploying to main from @ amaranth-lang/amaranth@4da8adf7ba8c2d4994c3af46137e0f07186e908e 🚀
<cr1901>
jfng[m]: Just to let you know ahead of time... won't be here for Friday's meeting. I had a doctor's appt in the morning, and they had to reschedule it to when the meeting takes place. How convenient.
<_whitenotifier-3>
[amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1070-4da8adf7ba8c2d4994c3af46137e0f07186e908e - https://github.com/amaranth-lang/amaranth
johninbaltimore has joined #amaranth-lang
<johninbaltimore>
is there any current work on getting the simulator to work with verilog/vhdl?
<_whitenotifier-c>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 0e65ddf - Deploying to main from @ amaranth-lang/amaranth@357ffb680cefa497469eb4f3cf25b83fd11a2796 🚀
<whitequark[cis]>
<johninbaltimore> "is there any current work on..." <- yes; cxxsim (currently in a branch that's fairly out of date and not ready to use generally) will do this
<whitequark[cis]>
<johninbaltimore> "And can you currently step or..." <- currently no; however I am working on enabling CXXRTL, the engine behind cxxsim, to have a debugging protocol, and we (ChipFlow) have a (not available to general public yet) prototype of a VS Code extension that can use it
<johninbaltimore>
nice
<johninbaltimore>
I'm very interested in an EDA tool that can do VCD display with interactive step through
<johninbaltimore>
though truth be told I'm really highly interested in an EDA tool that can simulate a Pi Pico, including its PIO (Wokwi can), while also simulating a chip that's connected to the Pico—which is probably not something anyone here is working on
<whitequark[cis]>
what kind of interactive step through? are you imagining a line-by-line stepping, or time-point-by-time-point?
<johninbaltimore>
for something reasonable like integrating a Python source editor with a live VCD viewer? You can do line by line, Vivado does, but I'm not sure how. I guess you'd need to somehow tag the netlist with the relevant source code line. Seems complicated.
<johninbaltimore>
Time point or just on a certain signal transition (like a clock) seems simple by comparison
<whitequark[cis]>
Amaranth already does this
<whitequark[cis]>
* does this (tags the netlist with source code lines)
<johninbaltimore>
the problem is line by line is actually useful
<johninbaltimore>
oh
<johninbaltimore>
then line by line might be relatively easy to implement as it stands
<johninbaltimore>
versus like, having no infrastructure to even begin to attempt that
<whitequark[cis]>
anyway, the thing about line by line is that I feel it's not useful in gateware context, since things execute in parallel, not serially
<whitequark[cis]>
meanwhile time point by time point is well represented if you have a proper simulator
<johninbaltimore>
I've actually used the line stepping and breakpoints heavily in vivado
<whitequark[cis]>
you might be quite pleased with the contents of that gist
<johninbaltimore>
there's a point where I can look at a signal and go oh, that showed up late, I know why it did that
<johninbaltimore>
but then there was that time I was trying to write a binary division circuit and uh. I did a lot of breakpointing at particular source code lines and then scratching my head like wait, why does it give me a result different than what I expected?
<whitequark[cis]>
oh, I do plan to add breakpoints to the VS Code extension. it's just that a breakpoint will be basically a UI presentation for searching the simulation database for a certain event
<whitequark[cis]>
trying to treat the contents of always_comb or something as serially executing code isn't a particularly great idea
<johninbaltimore>
oh wow
<johninbaltimore>
you built it on replay
<whitequark[cis]>
yes
<johninbaltimore>
that's…setting up for an unusually powerful debugger
<whitequark[cis]>
i designed and implemented the simulator, the record/replay interface, the capture of $display and assert/etc statements, and the JSON server which can use all of the above
<johninbaltimore>
with vivado it was always figure out where it's giving me the wrong result, breakpoint where I think it's breaking and watch how each thing changes until it does something I didn't expect, make a change, restart the *entire simulation*
<johninbaltimore>
sometimes run to a point, decide I've gone past where I think it's broken, restart the simulation and run to an earlier point, and feel around trying to find out what might be broken
<whitequark[cis]>
the simulator engine has an interesting property, which is that it provides you with 100% coverage of public names in the design and it runs at roughly the same speed as Verilator
<johninbaltimore>
nice
<johninbaltimore>
how does it run when you put it on pypy
<whitequark[cis]>
no more hunting for your signal and then placing (*keep*) to find out what it does
<whitequark[cis]>
oh, the simulator is a Yosys backend written in and emitting C++ code
<johninbaltimore>
oh ok
<johninbaltimore>
I thought the current simulator was pure python
<whitequark[cis]>
the Amaranth simulator is pure Python
<whitequark[cis]>
in the cxxsim branch, it's extended to provide the same Python testbench interface but run the RTL in compiled C++ code
<johninbaltimore>
nice
<whitequark[cis]>
the simulator has a C ABI that can be used for design introspection
<johninbaltimore>
(I'm slightly surprised someone is writing new code in C++, rust or something seems to be all the rage today)
<whitequark[cis]>
it's very interesting C++ code too
<johninbaltimore>
tbh I can't understand most complex software
<whitequark[cis]>
the main eval function is annotated in such a way that every other function in it is inlined, because the arbitrary width arithmetics is implemented entirely using template metaprogramming
<whitequark[cis]>
so I have like a normal for loop doing chunk-by-chunk addition, and then clang translates this to just a single add instruction if it's within 64 bits, with a mask maybe
<johninbaltimore>
I'm getting a box with an X in it before some of these words
<whitequark[cis]>
I'm using monospaced text and your IRC client doesn't know how to render the control code that starts it
<whitequark[cis]>
this is the core of the simulator runtime. it's less than 2000 lines. together with the backend, which is less than 4000 lines, it's competitive with Verilator
<johninbaltimore>
I wonder how fast it can simulate a small RISC-V CPU running Minix, which is also 4000 lines of code
<whitequark[cis]>
it can run Minerva, a 32-bit RISC-V core, at around 1 MCPS
<johninbaltimore>
in any case this will enable adding VHDL/Verilog code along with straight Amaranth? That's a big, huge step forward
<whitequark[cis]>
on my laptop (model name : Intel(R) Core(TM) i9-9880H CPU @ 2.30GHz), in max performance mode (turbo boost enabled, etc)
<johninbaltimore>
it means I can simulate e.g. a gameboy using tv80 without having to write my own z80 core in Amaranth
<whitequark[cis]>
yeah the goal is for you to be able to add Verilog files to your simulation and be able to debug the combined thing in your editor, where clicking on a signal shows you the Verilog or Amaranth source code at the point of definition
<whitequark[cis]>
VHDL too, provided you compile Yosys with VHDL support (I think oss-cad-suite enables it. I don't because I really dislike using GNAT)
<johninbaltimore>
I'm guessing this is more of a "Coming sometime soon" thing than a "coming in 10 years maybe" thing
<whitequark[cis]>
year-ish?
<johninbaltimore>
that soon? Damn
<whitequark[cis]>
this is the culmination of a multiple year project I had, whose goal is to drag EDA, kicking and screaming, into the 21st century
<johninbaltimore>
Deleting the part of my book that clumsily explains how to install Thonny with Pypy
<whitequark[cis]>
you do get some benefit from using PyPy for the pure-Python simulator, and it will remain, it's useful
<whitequark[cis]>
tbh, I wonder if using CXXRTL to translate just the Verilog code, and PyPy or something to translate Amaranth code, and then cosimulating them, would be beneficial compile time wise
<whitequark[cis]>
CXXRTL is great but it has compile times that can get pretty high
<whitequark[cis]>
you'll also get things like Print statements in Amaranth that translate to $display Verilog cells and work in simulation
<johninbaltimore>
yes but the process for getting Thonny in PyPy if you're on Windows is essentially download a Zip file, get on a command line, run pypy to create a venv, then manually activate the venv, pip install thonny, and then always activate the venv from the command line and run thonny from there
<whitequark[cis]>
and Assert statements in Amaranth that translate to SVA assertions and have a message attached to them that lets you get an overview of the signals in question
<whitequark[cis]>
and eventually I want to make it so that if you run your testsuite in a VS Code terminal, and an assertion fails, you would get instantly dropped into the RTL debugger, stopped at that time point and line
<johninbaltimore>
the wokwi project above runs MicroPython on a simulated raspberry pi pico, if you run it a PIO tab pops up that shows the running state of the programmable IO state machines and everything. There's actually a project that outputs sound, too
<whitequark[cis]>
run yosys in vscode! run nextpnr in vscode!! run openfpgaloader in vscode!!!
<whitequark[cis]>
i do want to run clang in vscode too, to compile cxxrtl generated code, eventually
<johninbaltimore>
I'd like to one day see EDA tools that go so far as to have a simulator like that, integrated with a simulator for Amaranth/VHDL/Verilog, with the ability to connect them together into one design so you can make a chip design and make the firmware to control it and simulate the whole thing
<whitequark[cis]>
cxxrtl supports black boxes so you can kinda do this today already
<whitequark[cis]>
it's not fully integrated yet, but you can integrate arbitrary C++ code with the output of CXXRTL
<whitequark[cis]>
(you can also already integrate arbitrary Python code with the Amaranth simulator, but it's a tad slow)
<johninbaltimore>
yeah, it'd require figuring out which is accessing a signal at what time for input/output though
<johninbaltimore>
like if the pico pulls a data line high at 7.9ns and the design reads that data line at 8ns it'd need to find that line high, the timing has to be matched up exactly
<johninbaltimore>
so you have two simulators with different timings trying to decide which is doing what first
<_whitenotifier-c>
[amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1071-357ffb680cefa497469eb4f3cf25b83fd11a2796 - https://github.com/amaranth-lang/amaranth
<whitequark[cis]>
that's just cosimulation
<johninbaltimore>
honestly I have no idea how difficult of a problem that is
<whitequark[cis]>
if you set a signal and read it at exactly the same virtual simulation time, you can have a race condition potentially
<whitequark[cis]>
however, if you do this in real hardware, you also have a race condition, which can result in metastability
<johninbaltimore>
Buu said you need a 4GHz machine to simulate a 3MHz NES because cosimulation is super hard
<johninbaltimore>
I always found that suspect because I just see it as a cooperative multitasking process but what do I know anyway
<whitequark[cis]>
it's not cosimulation that's hard, but simulating a gate level netlist
<johninbaltimore>
oh, he was talking about software emulators
<whitequark[cis]>
cosimulation is just a fancy way of saying you have coroutines acting on shared state formatted in a certain way
<johninbaltimore>
like making sure that when the CPU accesses the PPU bus it does so on the PPU clock cycle the PPU will actually be on
<whitequark[cis]>
yes, I know
<johninbaltimore>
I don't know why that's a hard problem
<whitequark[cis]>
with those old consoles it's generally tricky to emulate them because they often rely on weird tricks in their implementations we don't use anymore
<johninbaltimore>
true
<whitequark[cis]>
Amaranth is heavily geared towards fully synchronous logic for example, while lots of these old chips do things asynchronously
<whitequark[cis]>
if things only happen on a clock edge you can safely do nothing unless there's a clock edge
<johninbaltimore>
yeah…things got bizarre when I tried to write PIO to control an AY-3-8910 and realized the register interface wasn't just timed to the clock, but was just a very slow latch
<johninbaltimore>
like the clock is 4MHz and it generates 4 million samples per second but it needs 1800ns to write data to the configuration registers
<whitequark[cis]>
CXXRTL actually does struggle with cosimulation in some cases, but it's less because it's a hard problem inherently, and more because the semantics of async signals aren't well defined in yosys
<whitequark[cis]>
so there is ambiguity about exactly what to do when you have edge triggered logic and there's no one to resolve it
<whitequark[cis]>
Verilog and VHDL do resolve the ambiguity but at such a high cost that virtually no one actually wants it
<_whitenotifier-c>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] a3fa3aa - Deploying to main from @ amaranth-lang/amaranth@b5f0295bf47d2b4db47f86da6edd7db4abb132c6 🚀
<johninbaltimore>
Vivado throws warnings if you create latches in Verilog or VHDL
<whitequark[cis]>
AY-3-8910 might be using a bucket brigade device to store the register contents instead of having a normal synchronous D-flop
<johninbaltimore>
it's using a level-sensitive latch as far as I can tell
<whitequark[cis]>
basically might have a long circular shift register which syncs up each 1800 ns with the input on the data bus
<whitequark[cis]>
I know YM3812 does that
<johninbaltimore>
interesting
<whitequark[cis]>
kevtris reverse engineered that one so you can just go look at the verilog code
<whitequark[cis]>
or was it jotero? it was jotero i think
<johninbaltimore>
so I'm in linear algebra class now AND Calc 2, and the linear algebra teacher is like "yeah you aren't going to understand that until you take control theory"
<johninbaltimore>
like…what's control theory?
<johninbaltimore>
I have never heard of this before
<johninbaltimore>
I think that's the read/write signal on the control bus
<whitequark[cis]>
oh yeah but it controls the latch
<johninbaltimore>
yeah
<whitequark[cis]>
there is a pdf schematic but it breaks every reader i've tried
<whitequark[cis]>
the timings tell you how to use it but they don't tell you why
<johninbaltimore>
on 5-24 it has the table for all the timings. the BC signals are all 50ns, writing the address takes a total 350ns, and writing data takes 1800ns
<johninbaltimore>
which is what I don't get
<johninbaltimore>
the chip is clocked for 250ns cycles but you need to select data write on BC and hold the data on the DA bus for 1800ns
<johninbaltimore>
and those buses aren't synchronized with the clock
<johninbaltimore>
as far as I can tell, BC/BDIR are the signals that open and close the latches
<johninbaltimore>
except i think the addresses might be latched but the data might be in a different kind of register (maybe synchronous?)
<johninbaltimore>
btw the timing is MUCH different on the 8930 and YM2149
<johninbaltimore>
in any case yeah, it doesn't tell you why
<johninbaltimore>
and I have no idea what's going on inside that chip
<galibert[m]>
Sounds more like signal processing than control theory
<galibert[m]>
FWIW in the yamaha chips the rotating shift registers are used only for the FM (and later PCM) parts of the chip. The PSG part is independant on the die (mostly) and does not rotate iirc
<galibert[m]>
Looks very different too
<galibert[m]>
https://og.kervella.org/ym2203/ym2203/ for instance, PSG is the bottom right, FM is... everything else, you have a good example of the shift registers top left
<omnitechnomancer>
Yea the shift registers are how they manage to not need an unreasonable number of NCOs by time domain multiplexing the one oscillator and other related stuff
jjsuperpower has quit [Read error: Connection reset by peer]
jjsuperpower has joined #amaranth-lang
Chips4MakersakaS has quit [Quit: Idle timeout reached: 172800s]
<_whitenotifier-3>
[amaranth] whitequark opened issue #1074: Add an `amaranth.hdl._ast.Matches` node, use it for `Value.matches`, and delegate from `Case()` to `Value.matches` - https://github.com/amaranth-lang/amaranth/issues/1074
<_whitenotifier-3>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] ff1f0a2 - Deploying to main from @ amaranth-lang/amaranth@115954b4d957b4ba642ad056ab1670bf5d185fb6 🚀
<galibert[m]>
great, I'm utterly failing at GroupXIV