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<nates93[m]>
btw the new logo is awesome
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<cr1901>
http://gopher.wdj-consulting.com:70/paste/12177c69-5b38-4d13-9b0b-f615e74fbc1d.txt Am seeking help rewording the "`Top` exposes" paragraph. I believe it's technically correct, but I don't like my word choices (clk and rst "belong to" a clk domain, rather than "are exposed" in an interface... How might I reword this to be better?)
<cr1901>
FWIW, I am comparing/contrasting with Verilog generation for someone new to Amaranth but familiar w/ Verilog. Verilog _will_ directly expose clk and rst as part of the port list/interface to outside world.