<_whitenotifier>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 4a0d727 - Deploying to main from @ amaranth-lang/amaranth@9e9790377aed250a8c95937982c70e6a42465a3a 🚀
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<key2>
seams like something is broken in verilog generation on yosys 0.37 my code generated from 0.35 works but not 0.37 :/
<whitequark[cis]>
that's possible. could you bisect yosys, please?
<key2>
what do you call bisect ?
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<key2>
so far I don't know what triggers the bad generation, as the module that I am generating has some fifo, fsm, Records...
<whitequark[cis]>
git bisect
<key2>
so I'll have to break it in piece until I find out what the difference is. but since in one case yosys generates "cases" and in the other one "if" it's not easy to diff
<key2>
ah ok
<key2>
I didn't know git had a bisection system ;)
<_whitenotifier>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 55eb35a - Deploying to main from @ amaranth-lang/amaranth@b40c18fb008c2dc68d2dc600dd667213369d876f 🚀
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